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488 Views
Registered: ‎07-15-2019

sobel edge detection design

I want to make a sobel edge design on Pynq Z2 without the zynq proccessor system but i have timing error.

 

sobel.jpgconstraints3.jpgmessages1.jpg

sobel.jpg
6 Replies
Teacher drjohnsmith
Teacher
477 Views
Registered: ‎07-09-2009

Re: sobel edge detection design

I cant read the errors very well, way to small,
but the first one seems to be about the clock circuit, and outside its valid range,

Id suggest you sort that first, and see what happens.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
475 Views
Registered: ‎06-21-2017

Re: sobel edge detection design

When you created the Clocking Wizard, did you enter the correct input clock period, that is the real sys_clk period?  The clock wizard will not set up a MMCM or PLL with a VCO out of range providid you give it good information.

0 Kudos
372 Views
Registered: ‎07-15-2019

Re: sobel edge detection design

i set the board interface of clk_in1 as "sys clock", in clocking options i chose MMCM , input frequency 125MHz and output 100MHz.

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Explorer
Explorer
319 Views
Registered: ‎06-09-2015

Re: sobel edge detection design

auto.giannis@gmail.com  have you solved the issue? Here is the clocking wizard configuration taken from Zybo Video Workshop-Digilent.

clocking wizard config.PNG

You also need to configure "DVI to RGB Video Decoder" as explained in Page 23. I hope it will help you!

Regards,
krishna@logictronix.com
0 Kudos
294 Views
Registered: ‎07-15-2019

Re: sobel edge detection design

Thanks for your reply, i did that but the same errors occurs.

0 Kudos
236 Views
Registered: ‎07-15-2019

Re: sobel edge detection design

I found the solution,

I had to remove the lines 187,188,189 and change the constraints names according to the design wrapper.

These are the correct archives.
sobel.jpgconstraints.jpg