01-08-2020 09:45 AM
I want to make a sobel edge design on Pynq Z2 without the zynq proccessor system but i have timing error.
01-08-2020 10:08 AM
01-08-2020 10:12 AM
When you created the Clocking Wizard, did you enter the correct input clock period, that is the real sys_clk period? The clock wizard will not set up a MMCM or PLL with a VCO out of range providid you give it good information.
01-09-2020 07:46 AM
i set the board interface of clk_in1 as "sys clock", in clocking options i chose MMCM , input frequency 125MHz and output 100MHz.
01-15-2020 09:15 PM
01-25-2020 05:46 AM
I found the solution,
I had to remove the lines 187,188,189 and change the constraints names according to the design wrapper.
These are the correct archives.