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Explorer
Explorer
5,152 Views
Registered: ‎12-21-2009

static timing report

Hi all

i was compiling a design using virtex-5 ISE10.1, generated the post place & route static timing report setting report unconstrained paths to 1 to allow the tool to report the maximum combinational path delay after PAR

 

in the first time compilation this was a sample from the report

 

Delay:                  17.423ns (data path)

SLICE_X77Y47.CMUX    Taxc                  0.261   EB_minus_EA_minus_LZb_m1/vCs<2>
                                                                          LZa_lt_abs_EA_minus_EB_f7
    SLICE_X74Y53.B2      net (fanout=12)       1.125   LZa_lt_abs_EA_minus_EB
    SLICE_X74Y53.B       Tilo                         0.080   N131

 

 

I did some modifications for the bold signals and reimplemented the design

the bold signal did not appear again in the critical path but another net appeared and here is the new report sample

 

 SLICE_X66Y49.B3      net (fanout=21)       2.472   N103
    SLICE_X66Y49.B       Tilo                  0.080   N197

 

 

then these nets N197 and N103i don't know which part of the code that i could modify to minimize their delays and also i want to know the meaning of those symbols  => Tilo , Tioop and so on

 

Any suggestions ?!!!!

thanks in advance :D

 

 

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1 Reply
Observer pboxall
Observer
5,045 Views
Registered: ‎10-21-2008

Re: static timing report

They might be signals inferred by the synthesis tool from your code. A good way to view them would be via FPGA editor for example (cross probing the path from TA is useful), or in timing analyser right mouse on the path and select 'view in technology viewer' (or something like that) to look at the whole path. Not sure if this is available in 10.1.

 

Tilo is the logic delay through a LUT, Tioop is the delay from the O pin to the IOB pad through the output buffer of an IOB pad. You can find out what all these timing names mean from the switching characteristic guide. For Virtex-5: http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf

 

You cant reduce the Logic delay in the path unless you were to pipeline your code to reduce the number of logic levels. The routing is dynamic and depends on how far the instances are placed apart for example. Generally hte higher the fanout the harder it might be to reduce the routing (ie moving the source closer to one destination might increase the routing delay to another destination).

Regards
Peter Boxall
Managing Director
Black Box Consulting
Xilinx Authorised Training Provider
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