We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎10-12-2016

synchronous inter clocks timing constraints ?

Hi Friends,

I have few clock generating from same clock source, how to constraint them for setup and hold. i used set_multicycle_path for some clocks which are in relation like clk60M to clk240M.

what are synchronous inter clocks timing constraints for different frequencies ?


For any help or suggestions are highly appreciated.

Thank You

S Sampath

0 Kudos
1 Reply
Registered: ‎07-18-2018

Re: synchronous inter clocks timing constraints ?

Hi ssampath,

   Are you asking about crossing between domains that are not multiples of eachother?

It depends how your logic is handling the crossing. If you are going from 100 to 200 or 200 to 100 and the logic knows that it's only receiving data every other cycle or vise versa, then a multi cycle is fine.

But if you have a domain producing data at 53 but consuming at 67, you likely will need logic to synchronize such as a fifo. Otherwise even if you found a multi cycle that closed timing (Which since they are synchronous can be possible) , you would only be sure that the data from a launch edge of one clock domain was correctly captured on the other domain, but not that it functions as expected.

It might be helpful to have an example of a particular path between clock domains that are different frequencies that you need to cross compared to what the logic for the crossing looks like.

0 Kudos