timing contraint for real time hardware co-simulation
I'm trying to use virtex 4 board (with vc4sx35 fpga) to test an algorithm using co-simulation in real time. I put 50 ns (20 Mhz) in the system generator token. The design has passed all timing contraints and the co-simulation block is created.
In the design, there are upsampling and downsampling, so the some parts of the design is running at low as 3.33Mhz, if I want to test the algorithm with hardware co-simulation on free-running clock, Do you think there be a problem because of the low frequency?