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Explorer
Explorer
13,968 Views
Registered: ‎08-23-2011

timing score = 0, all constraints met, but .twx report shows some failing paths ...

<reposting on the appropriate forum>

 

hi,

 

im using xilinx 14.1 for some design implementation. design is implemented properly - translate, map, par all pass.

reports are clean.

par report has no timing error. design summary shows all constraints met and timing score = 0. 

 

but the .twx report has some failing paths with setup/hold issues.

 

eg (hold path) - 

Slack (hold path): -0.012ns (requirement - (clock path skew + uncertainty - data path))
Source: top/bm_top/i2c_bm_wdata_d[0] (FF)
Destination: top/vou_top/vou_vf0/vf1_gm_G/lv_gamma_ram/ram_ram_0_0 (RAM)
Requirement: 0.000ns
Data Path Delay: 0.383ns (Levels of Logic = 0)
Clock Path Skew: 0.181ns (1.588 - 1.407)
Source Clock: clkgenout[0] rising at 0.000ns
Destination Clock: clkgenout[2] rising at 0.000ns
Clock Uncertainty: 0.214ns

 

eg (setup path) -

Slack (setup path): -0.228ns (requirement - (data path - clock path skew + uncertainty))
Source: top/bky_reg/r_vsc_h_num[4] (FF)
Destination: top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/gpix_dp/rsum0[12] (FF)
Requirement: 10.000ns
Data Path Delay: 9.962ns (Levels of Logic = 4)
Clock Path Skew: -0.052ns (3.230 - 3.282)
Source Clock: clkgenout[0] rising at 0.000ns
Destination Clock: clkgenout[2] rising at 10.000ns
Clock Uncertainty: 0.214ns

 

NOTE - in the above source/destination paths, for setup and hold, clock domain crossing is happening.

 

Questions - 

 

 

1) so i wanted to know that if the timing score = 0 and the design is implemented and no timing errors show up in PAR report, then should we still bother about the above failing constraints in the .twx report?

 

2) in another thread, i read that such hold path violations, if a CDC is happening, then it can be overlooked. is that correct?

 

3) Would the same apply for setup violations?

 

4) Is the design considered fine and "properly implemented" if the timing score is 0 and map/PAR pass without errors even though we have the above sort of timing messages in the .twx report?

 

please let me know ...

 

z.

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10 Replies
Instructor
Instructor
13,955 Views
Registered: ‎08-14-2007

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

In the timing report, do these paths show up in "Unconstrained" paths?  I've seen that TIG paths are still analyzed in the post place&route timing report if you enable reporting of unconstrained paths.  Since the place & route didn't report errors, it's likely that this is the case.

-- Gabor
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Explorer
Explorer
13,952 Views
Registered: ‎08-23-2011

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

hi gszakacs,

 

thanks for your reply.

 

i am not using any TIG constraint in my UCF file. so how do i check if these paths are unconstrained or not? anything that i can look for in the .twx file. my ucf file only has the i/p clock constraint of 100M.

 

i know that the paths i mentioned are going through a CDC so i am not sure if the hold/setup errors on them is becuase they cross clock domains? 

 

do i need to worry about failures on unconstained paths or paths that go through a CDC?

 

if the above is true, what is the best constraint that i should put in the ucf for the above?

 

thanks for your help in advance,

z.

 

 

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Xilinx Employee
Xilinx Employee
13,929 Views
Registered: ‎07-16-2008

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

What Gabor suggested is to check whether the TRCE option -u is enabled.

trce_unconst.png

 

By default, it's turned off.

 

Note the hold violations from unconstrained paths contribute to the timing errors in trce report. But in PAR report and Design Summary, only constrained paths are taken into account.

http://www.xilinx.com/support/answers/37292.html

 

In ISE, unless the two clocks are related (automatically propagated by tool or manually by constraint), the CDC path is not analyzed. If these paths can be ignored, you can ignore the additional errors in the unconstrained path, or to add TIG to remove them from unconstrained path.

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Explorer
Explorer
13,917 Views
Registered: ‎08-23-2011

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

hi graces,

 

thanks for your reply.

 

i checked and the reporting for unconstrained paths is turned off in my ISE, i.e. that field is blank.

 

as for the 2 clocks, since they are coming from the same PLL and are the 20M and 80M o/p of the PLL, would one say that these clocks are related? the path on which the violation occurs is from 20M(source) to 80M(destn).

 

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
13,911 Views
Registered: ‎07-16-2008

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

For the two clocks generated from the same PLL, the tool will automatically derive period from the PLL input. In that case, they're related and the CDC path is covered by timing analyzer.

 

Can you attach the timing report (.twx/.twr) for a look?

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Explorer
Explorer
13,899 Views
Registered: ‎08-23-2011

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

hi,

 

here's the error in the timng report ... it's just one path now.

 

this is still a CDC source - destination.

 

wanted to know which constraints can i apply on such paths to resolve the timing issues? any other strategies in constraining/tool settings that i can adopt (cause changing code around is not an option).

 

...

Hold Paths: TS_TABULA_clkgen_V0_clkout2 = PERIOD TIMEGRP "TABULA_clkgen_V0_clkout2"
TS_clkref_p / 0.8 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YPM2_coff/r_coff[2] (SLICE_X74Y45.B1), 1 path
--------------------------------------------------------------------------------
Slack (hold path): -0.014ns (requirement - (clock path skew + uncertainty - data path))
Source: toshiba_top/bky_reg/r_vsc_hcy41[2] (FF)
Destination: toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YPM2_coff/r_coff[2] (FF)
Requirement: 0.000ns
Data Path Delay: 0.363ns (Levels of Logic = 1)
Clock Path Skew: 0.096ns (1.549 - 1.453)
Source Clock: clkgenout[0] rising at 0.000ns
Destination Clock: clkgenout[2] rising at 0.000ns
Clock Uncertainty: 0.281ns

Clock Uncertainty: 0.281ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.315ns
Phase Error (PE): 0.120ns

Minimum Data Path at Fast Process Corner: toshiba_top/bky_reg/r_vsc_hcy41[2] to toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YPM2_coff/r_coff[2]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X74Y40.CQ Tcko 0.098 toshiba_top/vsc_hcy41[3]
toshiba_top/bky_reg/r_vsc_hcy41[2]
SLICE_X74Y45.B1 net (fanout=3) 0.267 toshiba_top/vsc_hcy41[2]
SLICE_X74Y45.CLK Tah (-Th) 0.002 toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/HCY_PM2[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YPM2_coff/r_coff_18_10[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YPM2_coff/r_coff_18_15mux_RNO_0[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YPM2_coff/r_coff_18_15mux[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YPM2_coff/r_coff[2]
------------------------------------------------- ---------------------------
Total 0.363ns (0.096ns logic, 0.267ns route)
(26.4% logic, 73.6% route)

 

 

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13,857 Views
Registered: ‎02-28-2011

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

If the 20M and 80M clocks are from the same source, then you should not get this timing error. Like already said those clocks should be related and the tools will add constrints automatically.

It looks like your clocks are not related. Check your clock generator settings. Especially group, phase shifts and buffer type etc. Settings for both clocks should be the same.

 

Regards Markus

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Explorer
Explorer
13,848 Views
Registered: ‎08-23-2011

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

hi, 

 

i checked the PLL and the 20 and 80M are coming from the same PLL - so like you say - they are related.

 

i also checked the PLL setting and the 2 clocks are in the same phase w.r.t. the i/p clock and they are driving the same type of BUFG. 

 

in fact i am using default settings in the PLL apart for the clock o/p freq. so everything should be related ... is my understanding correct?

 

can i look at anything else to ensure that the clocks are not un-related or post something here to get it double checked?

 

z.

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Visitor elbadri
Visitor
11,851 Views
Registered: ‎06-16-2008

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

This sounds like a problem we have been struggling with for a while. Have you found a solution?

 

I'm thinking of using external loopback for my internally generated clocks and writing new constraints for them as if they are unrelated clocks!!??

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Xilinx Employee
Xilinx Employee
8,167 Views
Registered: ‎05-14-2008

Re: timing score = 0, all constraints met, but .twx report shows some failing paths ...

I don't agree with Markus. You see this timing error IS because the two clocks are related. Otherwise, if the two clocks are unrelated, this timing path won't be analyzed.

 

The problem I see is that you may need to apply a multicycle from-to constraint for this CDC path. It is a path from 20M to 80M, correct? So you need to constrain this path with from-to 50ns to relax the setup requirement. If you have other CDC paths similar like this, you'll need to multicycle constraints for those paths too.

 

With these multicycle constraints added, the tool may have more margin to resolve the hold error.

 

Thanks

Vivian

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