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Contributor
Contributor
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Registered: ‎06-17-2016

Hi

I'm studying UG903 and here are my questions.

At page 108 there is paragraph entitled "Important" but I think the figure isn't related to that paragraph.

I think the capture edge should move to right.

Capture.JPG

 

Am I right?

In the document the figure 5-9 is the same as figure 5-10, Is it possible to explain why the figures are the same?

 

1 Solution

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1,009 Views
Registered: ‎01-22-2015

Re: ug903

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@dariush84

     I think the capture edge should move to right.
You are correct. Good catch! In almost all the Xilinx documentation examples, you will see that registers (aka flip-flops) are sensitive to the rising-edge of the clock. That is, they will capture and launch data on the clock rising-edge. This is usually what you will see after implementation of your design because this is usually how we write our HDL code. For example, in VHDL, we almost always use “if rising_edge(clk)..” in a clocked-process and almost never use “if falling_edge(clk)..”.  You could use “if falling_edge(clk)..” if you want and this will result in a timing path where the clock is sent through an invertor before it reaches a register. However, this often leads to confusion and overly-tight timing requirements. Hence, it is not recommended.

     …figure 5-9 is the same as figure 5-10, Is it possible to explain why the figures are the same?
They are equivalent only because the CLK1 and CLK2 waveforms have the same frequency and are phase aligned. Therefore the time-relationship represented by the HOLD arrow in Fig 5-9 will be the same as the time-relationship represented by the HOLD arrow in Fig 5.10.

Good questions!
Mark

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Registered: ‎01-22-2015

Re: ug903

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@dariush84

     I think the capture edge should move to right.
You are correct. Good catch! In almost all the Xilinx documentation examples, you will see that registers (aka flip-flops) are sensitive to the rising-edge of the clock. That is, they will capture and launch data on the clock rising-edge. This is usually what you will see after implementation of your design because this is usually how we write our HDL code. For example, in VHDL, we almost always use “if rising_edge(clk)..” in a clocked-process and almost never use “if falling_edge(clk)..”.  You could use “if falling_edge(clk)..” if you want and this will result in a timing path where the clock is sent through an invertor before it reaches a register. However, this often leads to confusion and overly-tight timing requirements. Hence, it is not recommended.

     …figure 5-9 is the same as figure 5-10, Is it possible to explain why the figures are the same?
They are equivalent only because the CLK1 and CLK2 waveforms have the same frequency and are phase aligned. Therefore the time-relationship represented by the HOLD arrow in Fig 5-9 will be the same as the time-relationship represented by the HOLD arrow in Fig 5.10.

Good questions!
Mark

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Registered: ‎01-22-2015

Re: ug903

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@dariush84

That's all !?  No more questions?

Don't hesitate to ask.

Mark

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Registered: ‎06-17-2016

Re: ug903

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Hi Mark

Thanks a lot for your help.

I plan three steps to write a professional code according to methodologies:

1) studying UG903 and watching the related videos(done).

2) studying UG906 and watching the related videos(doing).

3) studying UG949 and watching the related videos(will do).

Now I'm studying ug906 and I have some questions.

UG906:

Q1:

On page 50, the document explains about  " Pulse with Report", What is the application of   " Pulse with Report" 

in a design?

 

Q2:

On page 55, The figure should be for maximum 4 path but it present for 10 and the figure is wrong, Am I thinking right?

Capture22.JPG

Q3:

On page 57, Is report datasheet useful for setting Input/Output delay?

 

Q4:

In some report wizards, there is a field as "Significant Digits" and the number default is 3.

I don't understand what is the usage of this field, Please explain about that.

 

Best Regards

 

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Registered: ‎01-22-2015

Re: ug903

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@dariush84

Thanks for your questions and for making an old teacher feel needed.

     I plan three steps…
Good plan! There are many fine Xilinx documents. I recommend adding UG901 (synthesis) and UG900 (simulation) to your study plan. UG901 gives many coding examples, using both Verilog and VHDL. You are encouraged to copy-and-use code from UG901. In fact, sometimes the UG901 code must be copied-and-used without modification in order to get what you want. Once you start writing (or copying) code, you will want to test it. UG900 describes how you can test your code using software simulation.

     What is the application of   " Pulse with Report"
If you have normal clocks (ie. not too slow, not too fast, and with 50% duty cycle) then you will probably never see problems in the “Pulse Width” report. This report indicates whether your design violates any of the physical limitations of hardware devices found in the FPGA. For more information about these physical limitations, you can read the data sheet for your FPGA (eg. DS182 for the Kintex-7 FPGA). There you will find that many FPGA devices have min/max specifications for clock frequency/period and for high-time/low-time width (ie. pulse width) of the clock. -see also pg225 of UG906.

     On page 55, The figure should be for maximum 4 path but it present for 10 and the figure is wrong, Am I thinking right?
You are correct! Since the “maximum number of paths per clock or path group (ie. N)” is set at 4 then Fig 2-22 should show only 4 paths (ie. only Path-1 through Path-4).

     On page 57, Is report datasheet useful for setting Input/Output delay?
Communications between the FPGA and an external device is called FPGA I/O. Making FPGA I/O work properly was (and still is) the most challenging part of FPGA work for me. I don’t use the Datasheet Report, but my reading indicates it is not the start for setting I/O delay – rather it is a report that lists all your I/O and whether each has passed timing analysis (ie. setup and hold slack are positive). The start for setting I/O delay is to gather information about the external device and the routing to the device. Then, this information is told to Vivado using timing constraints (eg. set_input_delay, set_output_delay), which you learned about in UG903. Writing these constraints correctly can be a challenge. You will find guidance from several places: 1) UG903, 2) posts by avrumw on this forum, 3) Vivado “Language Templates > XDC > Timing Constraints”, 4) Vivado Constraints Wizard

     In some report wizards, there is a field as "Significant Digits" and the number default is 3…. Please explain about that.
The Significant Digits field specifies the number of significant digits (to the right of the decimal) in the reported values. An example of a number with 3 significant digits is “1.234”. If you changed the reported significant digits to 1 then this number would become “1.2”. I can’t think of a situation where I needed more the 3 significant digits of accuracy in the Vivado reported values.

Mark

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Registered: ‎06-17-2016

Re: ug903

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Dear Mark

I appreciate your answers, they were very useful for me.

In RTL design, there is a top module that contains some components. The components work together according to a timing(control) signals. Usually, there is a timing generator component for generating timing signals for all components like Enable, Resets, an edge for syncing all components together.

 

Q1:

Is the above architecture good? Do you have a better suggestion?

 

Q2:

In the implementation of algorithms, we have some modes usually that each mode have its own timing or relationship. for example, in mode A the "Reg x" enable every 4 cycles but in mode B "Reg x" enables every 6 cycles, for such situations, How should I set multi-cycle path constraint?

 

Q3:

The multi-cycle path constraint should set between components or in each component?

 

Best Regards

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Registered: ‎01-22-2015

Re: ug903

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@dariush84

     Is the above architecture good? Do you have a better suggestion?
You have written a good overview of an RTL design.

     for example, in mode A the "Reg x" enable every 4 cycles ….. How should I set multi-cycle path constraint?
It is more correct to say multi-cycle path exception. We call it a timing-exception (rather than a timing-constraint) because it causes timing analysis to behave differently.  In contrast, a timing-constraint provides information needed by normal timing analysis.  For the register-enable situation that you describe, it is acceptable to let timing analysis behave normally. That is, if your circuit passes normal timing analysis then it will also pass timing analysis after you write the multi-cycle path exception. You only need the multi-cycle path exception if your circuit cannot pass normal timing analysis. Therefore, I suggest that you keep life simple and (for now) not use multi-cycle path exceptions.

Are you planning to program in VHDL?

Mark

Contributor
Contributor
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Registered: ‎06-17-2016

Re: ug903

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Hi Mark

Thank you.

I thought I must use timing exceptions along timing constraints when writing a component!!!

Are you planning to program in VHDL?

Yes, I studied "Volnei A. Pedroni-Circuit Design and Simulation with VHDL-The MIT Press (2010)" for learning VHDL. Do you have better suggestions?

 

BR

 

 

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Registered: ‎01-22-2015

Re: ug903

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@dariush84

     Yes, I studied "Volnei A. Pedroni-Circuit Design and Simulation with VHDL-The MIT Press (2010)" for learning VHDL.

I read some of this book online today.  It seems to be a very good book.  

Are you studying this book on your own or is it a textbook for your college class?

How far into the book have you read?

Contributor
Contributor
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Registered: ‎06-17-2016

Re: ug903

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Hi Mark
I only studied chapter one "I CIRCUIT-LEVEL VHDL" as my own and I use this book as a reference.
I'm studying UG906 now.

BR
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Registered: ‎01-22-2015

Re: ug903

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@dariush84

     I only studied chapter one "I CIRCUIT-LEVEL VHDL" as my own..
Oh my!  You are just starting a long and exciting journey.

    I thought I must use timing exceptions along timing constraints when writing a component!!!
You are correct – but let me explain. I doubt you will find much discussion of timing exceptions and timing constraints in your VHDL book – because they are not part of the VHDL language.  Exceptions and constraints are only needed when you try to place your VHDL-described circuit inside the FPGA.  That is, a VHDL programmer does not need to understand exceptions and constraints.  However, an FPGA engineer that is using VHDL must often write exceptions and constraints while writing VHDL.

     I'm studying UG906 now. 
For me, the hardest part of becoming an FPGA engineer was understanding timing analysis and learning how to solve timing analysis problems.  So, by reading UG903 and UG906, you are doing the hard part of your journey first.  No worries.  However, most of us learned to be a VHDL programmer before we learned to be an FPGA engineer.

So, if parts of UG903 and UG906 aren’t completely clear to you – no worries.  During your FPGA journey, you will often return to these documents (as I do) to relearn the concepts they discuss.  At this stage in your journey, I encourage you to focus most of your effort on becoming a very good VHDL programmer, which includes:

  1. Reading (and rereading) your VHDL textbook
  2. Learning to enter and organize your VHDL using Vivado HLx
  3. Learning to write testbenches (described in your VHDL textbook)
  4. Learning to test your VHDL components using testbenches and Vivado Logic Simulation (see UG900)

None of the above 4 tasks requires use of timing exceptions and timing constraints.

Enjoy the journey!
Mark

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Registered: ‎01-22-2015

Re: ug903

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@dariush84

I hope you will not hesitate to post questions about VHDL (you should probably create a new post for each question). You will find many people on the Forum who are eager to answer questions about VHDL.

Here, we celebrate many holidays this time of year – including the coming of a new year.  I wish you peace, joy, and success with your work in the new year.

Mark

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Registered: ‎06-17-2016

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Dear Mark

Happy new year and I hope the best for you.

Dariush

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