12-01-2018 11:14 PM
I took a small design and i use user clock divider logic with create_generate_clock and without create_generated_clock, i did not see any difference in the routing state and placement. in both cases vivado using BUFG after my user logic.
Then what is the use of this create_generated-clock ?
when it will useful exactly ?
NOTE: Any help or suggestions are highly appreciated.
12-01-2018 11:59 PM
12-02-2018 01:03 AM
what do you mean by stat points ? Can you pls elaborate more clearly ?
In my case experiment in both case routing happened same. anyway i will check it again.
12-02-2018 05:10 AM
Hi, @ssampath ,
Please check the 2 clock paths in your own example.
Clock Port -> BUFG -> MMCM -> clkou1:
To create clock for MMCM's clkou1 pin:
1. If you use create_clock on MMCM's clkou1 pin, the clock path will start from pin MMCM/clkou1
2. If you check let tool derive clock for MMCM's clkou1 pin (Create_generated_clock), the clock path will start from the "Clock Port", which is the port for its master clock.