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Adventurer
Adventurer
7,972 Views
Registered: ‎12-22-2008

why does Time Analyzer still analyze these paths after I set "TIG" attribute?

In my view, after set these paths "TIG", these paths will be ingored in Time analyzer, however it seem it isn't true. Why are these paths been analyzed after having been set "TIG"?
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6 Replies
Instructor
Instructor
7,944 Views
Registered: ‎08-14-2007

Re: why does Time Analyzer still analyze these paths after I set "TIG" attribute?

Can you give an example of "these paths" and the TIG constraint.  Normally a TIG constraint

is applied to an instance or net, not a "path".  The Timing Analyzer should ignore any paths

originating at the net or instance.  Placing a TIG on a flip-flop for example means to ignore

the time to propagate its Q to other loads in the design.  The TIG constraint will not prevent

the analysis of setup to the flip-flop's D input.  If you are having a problem setting up to

that flip-flop's D, and want to ignore the input setup timing, you need to place TIG constraints

on the sources of the D net.  If some of these sources should not be ignored generally,

you may instead need to add a FROM : TO time constraint.

-- Gabor
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Adventurer
Adventurer
7,937 Views
Registered: ‎12-22-2008

Re: why does Time Analyzer still analyze these paths after I set "TIG" attribute?

Thank you very much for your answer.

 

The problem is of the project about the ddr sdram controller which has been generated by MIG007. My situation is as the following:
In the ucf, there is constraint:

/////////////////////////////
INST "mem_interface_top0/infrastructure_top0/wait_200us" TNM = "wait200us";   //wait200us is the output register
INST "mem_interface_top0/infrastructure_top0/sys_rst*" TNM = "sysrst";
TIMESPEC TS01 = FROM "wait200us" TO "sysrst" TIG;


////////the end of the relevant content in the ucf

 

however, in the twx file, I see the relevant paths still being analyzed as follows:

 

/////////////the start of relevant content in the timing analyzer
Timing constraint: PATH "TS01_path" TIG;
 6 paths analyzed, 6 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
Delay:                  3.611ns (data path - clock path skew + uncertainty)
  Source:               mem_interface_top0/infrastructure_top0/wait_200us (FF)
  Destination:          mem_interface_top0/infrastructure_top0/sys_rst (FF)
  Data Path Delay:      3.589ns (Levels of Logic = 1)
  Clock Path Skew:      -0.022ns (3.244 - 3.266)
  Source Clock:         clk_int rising at 0.000ns
  Destination Clock:    clk_int rising at 8.000ns
  Clock Uncertainty:    0.000ns
  Constraint Improvement Wizard
  Maximum Data Path: mem_interface_top0/infrastructure_top0/wait_200us to mem_interface_top0/infrastructure_top0/sys_rst
    Location             Delay type         Delay(ns)                                 Physical Resource
                                                                                                     Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y42.YQ      Tcko                  0.374                      mem_interface_top0/wait_200us
                                                                                              mem_interface_top0/infrastructure_top0/wait_200us
    SLICE_X18Y58.G2      net (fanout=6)        1.206            mem_interface_top0/wait_200us
    SLICE_X18Y58.Y       Tilo                          0.313            mem_interface_top0/infrastructure_top0/sys_rst_o_not0001
                                                                                            mem_interface_top0/infrastructure_top0/sys_rst_1_or00001
    SLICE_X13Y59.SR      net (fanout=4)        1.113   mem_interface_top0/infrastructure_top0/sys_rst_1_or0000
    SLICE_X13Y59.CLK     Tsrck                 0.583   sys_rst
                                                       mem_interface_top0/infrastructure_top0/sys_rst
    -------------------------------------------------  ---------------------------
    Total                                      3.589ns (1.270ns logic, 2.319ns route)
                                                       (35.4% logic, 64.6% route)

--------------------------------------------------------------------------------
Delay:                  3.611ns (data path - clock path skew + uncertainty)
  Source:               mem_interface_top0/infrastructure_top0/wait_200us (FF)
  Destination:          mem_interface_top0/infrastructure_top0/sys_rst_1 (FF)
  Data Path Delay:      3.589ns (Levels of Logic = 1)
  Clock Path Skew:      -0.022ns (3.244 - 3.266)
  Source Clock:         clk_int rising at 0.000ns
  Destination Clock:    clk_int rising at 8.000ns
  Clock Uncertainty:    0.000ns
  Constraint Improvement Wizard
  Maximum Data Path: mem_interface_top0/infrastructure_top0/wait_200us to mem_interface_top0/infrastructure_top0/sys_rst_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y42.YQ      Tcko                  0.374   mem_interface_top0/wait_200us
                                                       mem_interface_top0/infrastructure_top0/wait_200us
    SLICE_X18Y58.G2      net (fanout=6)        1.206   mem_interface_top0/wait_200us
    SLICE_X18Y58.Y       Tilo                  0.313   mem_interface_top0/infrastructure_top0/sys_rst_o_not0001
                                                       mem_interface_top0/infrastructure_top0/sys_rst_1_or00001
    SLICE_X12Y59.SR      net (fanout=4)        1.113   mem_interface_top0/infrastructure_top0/sys_rst_1_or0000
    SLICE_X12Y59.CLK     Tsrck                 0.583   mem_interface_top0/infrastructure_top0/sys_rst_1
                                                       mem_interface_top0/infrastructure_top0/sys_rst_1
    -------------------------------------------------  ---------------------------
    Total                                      3.589ns (1.270ns logic, 2.319ns route)
                                                       (35.4% logic, 64.6% route)

--------------------------------------------------------------------------------
Delay:                  3.199ns (data path - clock path skew + uncertainty)
  Source:               mem_interface_top0/infrastructure_top0/wait_200us (FF)
  Destination:          mem_interface_top0/infrastructure_top0/sys_rst180_1 (FF)
  Data Path Delay:      3.179ns (Levels of Logic = 1)
  Clock Path Skew:      -0.020ns (3.246 - 3.266)
  Source Clock:         clk_int rising at 0.000ns
  Destination Clock:    clk_int falling at 4.000ns
  Clock Uncertainty:    0.000ns
  Constraint Improvement Wizard
  Maximum Data Path: mem_interface_top0/infrastructure_top0/wait_200us to mem_interface_top0/infrastructure_top0/sys_rst180_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y42.YQ      Tcko                  0.374   mem_interface_top0/wait_200us
                                                       mem_interface_top0/infrastructure_top0/wait_200us
    SLICE_X18Y58.G2      net (fanout=6)        1.206   mem_interface_top0/wait_200us
    SLICE_X18Y58.Y       Tilo                  0.313   mem_interface_top0/infrastructure_top0/sys_rst_o_not0001
                                                       mem_interface_top0/infrastructure_top0/sys_rst_1_or00001
    SLICE_X12Y61.SR      net (fanout=4)        0.703   mem_interface_top0/infrastructure_top0/sys_rst_1_or0000
    SLICE_X12Y61.CLK     Tsrck                 0.583   mem_interface_top0/infrastructure_top0/sys_rst180_1
                                                       mem_interface_top0/infrastructure_top0/sys_rst180_1
    -------------------------------------------------  ---------------------------
    Total                                      3.179ns (1.270ns logic, 1.909ns route)
                                                       (39.9% logic, 60.1% route)

--------------------------------------------------------------------------------
//////////////////////

So, I don't know why these paths are still being analyzer after the TIG constrait has been set.

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Instructor
Instructor
7,919 Views
Registered: ‎08-14-2007

Re: why does Time Analyzer still analyze these paths after I set "TIG" attribute?

It looks like you are generating a verbose timing report.  In this case all timing specs are analyzed

even though in the case of TIG specs there is no target to meet.  So of course there are no

timing errors and there is no reported "slack" for that constraint.

-- Gabor
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Adventurer
Adventurer
7,900 Views
Registered: ‎12-22-2008

Re: why does Time Analyzer still analyze these paths after I set "TIG" attribute?

Thank you for your answer firstly.

 

However, I still don't really understand  your words. What do you mean I am generating a verbose timing report? All the setting in my timing analyzer is default. Where can I find whether I am generating a verbose timing report or not. And I have checked my Option Tab of my timing analyzer and only "report paths by constraint" have been selected.

 

So, in this case, will the net which have been set "TIG"  be analyzered anyway? Do you mean those paths will be analyzed but will not influence the process of Place & Par?

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Instructor
Instructor
7,867 Views
Registered: ‎08-14-2007

Re: why does Time Analyzer still analyze these paths after I set "TIG" attribute?

If you run from the ISE GUI (project navigator), you can right click on the

process "generate post place&route static timing report" (working from

memory here, might be paraphrased).  Your options for the report type

are "Verbose" or "Error".  The error report will only show paths that

fail timing constraints.  The verbose report will show some number

of paths for every constraint whether or not the path met the constraint.

 

In your case, you have a constraint which you added just so you could

ignore a particular set of paths.  The fact that you defined this as a

timespec causes it to be listed in the constraints.  It is also possible

to use TIG by itself to generally ignore timing from a particular source.

This would have the form:

NET "foo" TIG;

or

INST "bar" TIG;

These are not considered constraints from the view of the timing analyzer and

therefore won't show up in the report.

 

As you have guessed, the TIG constraints in your project will not cause

place and route to be concerned with the specified paths.

-- Gabor
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Adventurer
Adventurer
7,857 Views
Registered: ‎12-22-2008

Re: why does Time Analyzer still analyze these paths after I set "TIG" attribute?

Now maybe I know what you mean: it is the way MIG adds this TIG constraint(TIMESPEC) makes it appear in the timing analysis. Thank you very much for your patience.

 

And I want to ask where I can know more about those things. Does cgd.pdf contain those information? In my view, if no one tells me about those things, maybe I cannot know how it works in this way. Thank you for your answer.

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