UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Participant pthomas
Participant
219 Views
Registered: ‎04-22-2015

AXI interface to Clocking Wizard

Jump to solution

Hello, I'm looking through pg065 and looking at the AXI registers in table 2-2, and looking at C_BASEADDR + 0x208, the desciption says "Bit[17:8] = CLKOUT0_FRAC Divide(3) Fractional part of clkout0 divide value For example, for 2.250, this value is 250 = 0xFA".

But I'm skeptical that this is actually a runtime writeable register. When I follow this through in a clocking wizard example design eventually it gets to a mmcm_frac_count_calc() call that seems to just be for initilization.

Can this actually be used in runtime? It would be very nice because it's a clean interface compared to the DRP register description.

thanks,

Paul

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
81 Views
Registered: ‎11-22-2016

Re: AXI interface to Clocking Wizard

Jump to solution

Open the IP example design for a clocking wizard IP core that has dynamic reconfiguration with an AXI interface (right-click on the IP core and select Open IP example design). The testbench for the example design writes all the registers and asserts and releases reset on the MMCM.

You can modify the testbench to write whatever values you want, then you can see the clocks after it comes out of reset.

0 Kudos
8 Replies
Xilinx Employee
Xilinx Employee
163 Views
Registered: ‎11-22-2016

Re: AXI interface to Clocking Wizard

Jump to solution

Yes, if you select Dynamic Reconfig in the clocking wizard GUI, by default an AXI-4 Lite interface is provided allowing run time configuration of the MMCM or PLL. In the GUI after Dynamic Reconfig is selected, you have the option of an AXI4-Lite or DRP interface.

 

0 Kudos
Participant pthomas
Participant
154 Views
Registered: ‎04-22-2015

Re: AXI interface to Clocking Wizard

Jump to solution

Yes, I understand that in general it is dynamically configurable (through C_BASEADDR+0x30X registers it seems). My specific question was about the C_BASEADDR + 0x208 register. If this is a dynamic register can you point me to the code path where this actually adjusts the MMCM? I only saw the initilize path when I looked through the example code, but if there is run-time code for the C_BASEADDR + 0x208 register I would like to use the same logic in a different design. It is frustrating to ask a very specific question and get a generic response back.

thanks,

Paul

0 Kudos
Xilinx Employee
Xilinx Employee
147 Views
Registered: ‎11-22-2016

Re: AXI interface to Clocking Wizard

Jump to solution

Yes, this is runtime configurable register. The MMCM's support dynamic clock divide changes without the need for resetting the MMCM. Refer to UG572 and the MMCM section of chapter 3.

0 Kudos
Participant pthomas
Participant
132 Views
Registered: ‎04-22-2015

Re: AXI interface to Clocking Wizard

Jump to solution

OK, I just tried this in simulation, and was not able to change the frequency, this example is attached. If this is possible then please demonstrate.

thanks,

Paul

0 Kudos
Xilinx Employee
Xilinx Employee
111 Views
Registered: ‎11-22-2016

Re: AXI interface to Clocking Wizard

Jump to solution

The original post was to the UltraScale Forum.

The example design you attached was incomplete (missing design files) and it was targetting an Artix-7.

7-series MMCM's must be reset in order for the updated clock register values to take effect.

UltraScale MMCM's support clock divide dynamic change, but not for the fractional divide. Additionally you must use the CDDCREQ and CDDCDONE signals along with the DRP interface.

The answer to your question is that the register at 0x208 can be written to during runtime, however the MMCM must be reset in order for it take effect.

 

 

0 Kudos
Participant pthomas
Participant
98 Views
Registered: ‎04-22-2015

Re: AXI interface to Clocking Wizard

Jump to solution

Yes, this is for UltraScale. I changed it to the ZCU102 board now. This time I used Project->Archive instead of Project->Write Tcl for the attached project.

I tried both a reset (writing 0x0000000a to C_BASEADDR +0x00) and the CDDCREQ without success.

Can you provide an example of 0x208 being written during runtime, and it changing the frequency?

Dynamically changing the fractional divide does work for the Ultrascale+, I'm using it! but direct through the DRP interface and not through the AXI reg 0x208 interface. However using the direct DRP registers is difficult in calculating everything correctly.

-Paul

0 Kudos
Xilinx Employee
Xilinx Employee
82 Views
Registered: ‎11-22-2016

Re: AXI interface to Clocking Wizard

Jump to solution

Open the IP example design for a clocking wizard IP core that has dynamic reconfiguration with an AXI interface (right-click on the IP core and select Open IP example design). The testbench for the example design writes all the registers and asserts and releases reset on the MMCM.

You can modify the testbench to write whatever values you want, then you can see the clocks after it comes out of reset.

0 Kudos
Participant pthomas
Participant
55 Views
Registered: ‎04-22-2015

Re: AXI interface to Clocking Wizard

Jump to solution

Thank you! this worked, the piece that I was missing was writing 3 to 0x25C, but it's there in the test bench if a little obfuscated.

This is all working in simulation correctly, hopefully it will be correct in the part.

thanks,

Paul

0 Kudos