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Visitor merlyn
Registered: ‎07-19-2018

BUG REPORT: Vivado 2018.3 / High Speed Select IO Wizard

Hope this is the correct place to post this...

It seems that when using HSSIO that the generated output hierarchy gets screwed up. synth folder contains file that should be in hdl folder and visa versa. This is a problem because now one must create custom IP to get the HSSIO into the block diagram and it pulls in the wrong files when doing so.

Which leads me to another question... In previous versions of vivado, you could implement the HSSIO module directly into the BD. (https://www.youtube.com/watch?v=DbxcTdP-sMM) Why did this change? 

This video explains how to generate an example IO loopback design using the UltraScale/UltraScale+ native mode High Speed SelectIO wizard. Features of the wizard are explained for both a TX and RX type of interface. An example design is created from a single interface that connects a complementary
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