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Cannot explain non-aligned PS-PL transfer issue.

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Visitor
Posts: 2
Registered: ‎10-06-2017

Cannot explain non-aligned PS-PL transfer issue.

Dear Users,

 

(Ubuntu 16.06, Vivado 17.2 64-bit, ZCU102 eval board (released silicon)).

 

I am seeing some strange behavior when attempting to write values from the PS-PL.

 

The data width of the interface HPM0_FPD is set to be 64-bit, and the transfers are all of type uint64_t to a region of memory mmap'd into user space (PS running Ubuntu 14.04).

 

In a sequence of non-burst write transaction (AWLEN=0) to incrementing 64-bit addresses, I am seeing WSTRB alternate between 0xFF and 0x00. 16-byte aligned transfers shown as having valid data, and other transfers being invalid.

 

Indeed the correct data is not read from memory and passed from PS-PL when the address ends ...XX08 (data should increment by 1 every transfer).

 

It is as if something in the PS thinks that the data width of the bus is 128-bit, and the non 16-byte aligned transfer is invalid.

 

I cannot explain this behavior without concluding that something is configured somewhere to think that the bus width is 128-bits, when in fact I have set it in the block diagram to be 64-bit. The hardware knows that only 64-bit is being transferred as AWSIZE is constantly 0x3.

 

Can anybody theorize how I might encounter this behavior given that I am not performing a burst transfer. Should I not always be transferring valid data under these conditions?

 

Many thanks,

 

Josh

 

 

 

 

 

 

 

 

C code to produce transfers:

 

for(uint64_t i = 0; i < config->datacount; i++) {

*(map + offset + i) = (config->data)[i];

}

 

 

Visitor
Posts: 2
Registered: ‎10-06-2017

Re: Cannot explain non-aligned PS-PL transfer issue.

Apologies, I could not embed the ILA waveform. Here it is...

ToXilinx.png