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Observer mustafaghanim
Observer
108 Views
Registered: ‎06-19-2019

How to implement ODDR2 in Vivado Block Design

I am trying to implement a VHDL RTL module of ODDR2 in Block Design for my FMC HDMI TX project with ZCU104. I am using Block Design to insert ODDR2 RTL module and connect its two inputs (clock_in and clock_in_not) to the outputs of my Clock Wizard. Furthermore, connecting its output ( clock_out) to my HDMI TX RTL module. 

My test design passes from synthesize, however it fails at "opt_desing" of implementation with this error:

 [DRC INBB-3] Black Box Instances: Cell 'tx_sys_i/oddr2/U0/i_oddr' of type 'tx_sys_clock_output_inverti_0_0_ODDR_BLACKBOX' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

The source of my ODDR2 VHDL code can be found at:

http://wiki.hevs.ch/uit/index.php5/Languages/VHDL/Examples/SynchronousBusXilinx

It was intended for Spartan-6 ISE. However, I think it should work for Vivado boards as well since it can be synthesized. 

I have to say that I have changed the "SIGNAL" type of clock_in_not  to an "INPUT" port for using my own Clock Wizard 180 phase shifted clock. I have tried not changing that signal type and keep it as default but I got the same result. 
These files are formed after running implementation:

1.png

The netlists are named as "BLACK BOX"

2.png

If it is not possible to solve this issue in a practical way, how can I implement ODDR2 with another design way?

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Scholar dpaul24
Scholar
83 Views
Registered: ‎08-07-2014

Re: How to implement ODDR2 in Vivado Block Design

@mustafaghanim.

It was intended for Spartan-6 ISE. However, I think it should work for Vivado boards as well since it can be synthesized.

I suspect a problem here. As I have understood, you are trying to use the ODDR from a series 6 in a newer FPGA device.

First question, which FPGA series are you using now?

There were vast changes from the 6 series to the 7 series and upwards. The ODDR being a Xilinx primitive has also undergone changes. So if my understanding is correct, you should update the ODDR instiantiation.

Get the latest version of UG768 and use the VHDL ODDR instiantiation templete there in you code.

Library UNISIM;
use UNISIM.vcomponents.all;
-- ODDR: Output Double Data Rate Output Register with Set, Reset
-- and Clock Enable.
-- 7 Series
-- Xilinx HDL Libraries Guide, version 14.2
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => Q, -- 1-bit DDR output
C => C, -- 1-bit clock input
CE => CE, -- 1-bit clock enable input
D1 => D1, -- 1-bit data input (positive edge)
D2 => D2, -- 1-bit data input (negative edge)
R => R, -- 1-bit reset input
S => S -- 1-bit set input
);

 

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