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Participant scmicron
Participant
810 Views
Registered: ‎08-23-2017

IDELAYE3 and IDELAYCTRL

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Dear all, in my design I need to instantiate an IDELAYE3 component, with associated IDELAYCTRL. The IDELAYE3 component is configured with DELAY_FORMAT set to TIME and DELAY_TYPE set to VAR_LOAD. The instance has DELAY_VALUE attribute set to 0x124 and a custom AXI interface to dynamically change the delay line through CNTVALUEIN and LOAD pins. According to UG571, the value statically set over DELAY_VALUE or dynamically changed through CNTVALUEIN is the desired delay in ps (plus some Align_Delay). In our simulations, I test the delay by triggering the Pad-to-Core delay path and reading the CNTVALUEOUT value by clearing EN_VTC (as per specifications). However, during simulation I see the following: - Pad-to-Core delay with default value (DELAY_VALUE attribute is 0x124): 0.359ns and value over CNTVALUEOUT is 0x3a - Pad-to-Core delay after CNTVALUEIN has been updated to 0x80: 1.127ns and value over CNTVALUEOT is 0x80 - Pad-to-Core delay after CNTVALUEIN has been updated to 0x124: 1.295ns and value over CNTVALUEOUT is 0x124 My question is: how to interpret the value over CNTVALUEIN? Am I missing something? Thanks in advance All bests S
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Community Manager
Community Manager
617 Views
Registered: ‎08-08-2007

Re: IDELAYE3 and IDELAYCTRL

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Which is better would depend on the System requirements. Either way the same amount of IDELAYCTRLs will be used in the design (one per nibble using at least one TIME mode delay element)

The approach of using one IDELAYCTRL and allowing Vivado to replicate is easier, however they you have one RDY signal that is all the RDY's AND'ed together. 

You need to follow the Reset Sequence and one of the steps is to wait for the RDY signal, so you will be waiting for all IDELAYCTRLs to be RDY.

If you have 4 Control Blocks then they may want it to be more granular, that each has its own RDY signal and can reset just that Control block. To do this you'd go back to the IDELAYCTRL within the Control Block and use the constraints. 

 

The error message says 

[Place 30-803] Clock region X2Y1 has 4 IODELAY_GROUPs

Meaning that the 4 Control Blocks are within the one clock region/bank, is that correct?

As long as the IOs in each Control Block don't try to share nibble that should be fine, you could try to LOC the 4 IDELAYCTRLs and see if that resolves the issue.

To check which nibble that IOs are, in the pin name there is the TxU or TxL

For example : IO_L22N_T3U_N7_DBC_AD0N_67 would be Byte 3 Upper Nibble. 

 

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13 Replies
Community Manager
Community Manager
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Registered: ‎08-08-2007

Re: IDELAYE3 and IDELAYCTRL

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Hi @scmicron

When you using TIME mode the value on the CNTVALUEIN and CNTVALUEOUT is the number of Taps, but the value on the IDELAY_VALUE is time / ns.

In simulation their is a default value for the Tap size.

I wrote this AR that may contain some details you find useful : https://www.xilinx.com/support/answers/66013.html

 

 From your details: 
DELAY_VALUE = 0x124 
 CNTVALUEOUT = 0x3a
Tap Size =  0x124/0x3a = 5ps so you know the simulation model is using a default tap size of 5ps.
When you update the CNTVALUEIN / CNTVALUEOUT to 0x80 that is a delay of (0x80 x 5ps) = 640 ps 
When you update the CNTVALUEIN / CNTVALUEOUT to 0x124 that is a delay of (0x124 x 5ps) = 1460 ps 
One very important thing to remember when using the VAR_LOAD is that you should not move by more than 8 taps at a time. Looking at your results I expect you are going directly from 0x80 to 0x124 and when you do that is delay line may shift into an unknown regions :https://www.xilinx.com/support/answers/67246.html
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Participant scmicron
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Registered: ‎08-23-2017

Re: IDELAYE3 and IDELAYCTRL

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@sandrao

Many thanks for the reply! Indeed good points.

Then if I am correct: since the delay I get when IDELAY has its static value (0x000 over DELAY_VALUE) is Xps, this is the "intrinsic" that I have to consider when applying a new value. Is that right?

Furthermore, if I had to instantiate more than one IDELAYE3 (in my case: 26), how many IDELAYCTRL shall I put? The documentation talks about "one IDELAYCTRL per nibble", but what does this mean?

Many thanks

Cheers

S

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Re: IDELAYE3 and IDELAYCTRL

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Hi @scmicron

 

If you measure the delay through the element when the DELAY_VALUE = 0 that is the intrinsic delay. I would expect different results from simulation and HW.

 

Vivado will replicate the IDELAYCTRL, so as long as you've one IDELAYCTRL is will replicate automatically.

If you are placing your IDELAYs in nibbles that already BITSLICE_CONTROLs used (i.e by MIG or the High Speed SelectIO Wizard) you need to create IODELAY_GROUP's as documented on Pg 199 of the UG:  http://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

 

Sandy

 

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Participant scmicron
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Registered: ‎08-23-2017

Re: IDELAYE3 and IDELAYCTRL

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Hi @sandrao

What if I just instantiate IDELAYE3 blocks and one IDELAYCTRL with no constraint? Shall I expect timing issues or is it enough for Vivado to close the design implementation?

Thanks

S

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Re: IDELAYE3 and IDELAYCTRL

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Hi @scmicron

 

 IDELAYE3 blocks and one IDELAYCTRL with no constraints should not be a problem. Vivado will route the same CLK to the REFCLK and then AND the RDY signals together to give the one RDY. 

I have not seen any timing issues on these paths. 

 

Sandy

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Participant scmicron
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Registered: ‎08-23-2017

Re: IDELAYE3 and IDELAYCTRL

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@sandrao

Perfect. Is an IDELAYCTRL required for ODELAYE3 as well? I couldn't find any ODELAYCTRL primitive.

Thanks

Cheers

S

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Re: IDELAYE3 and IDELAYCTRL

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Hi @scmicron

 

Its not the best name in the world. You need to use the IDELAYCTRL for either IDELAYs or ODELAYs that are in TIME mode.

Sandy

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Participant scmicron
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Registered: ‎08-23-2017

Re: IDELAYE3 and IDELAYCTRL

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Hello @sandrao

What if I have an IDELAYE3 and ODELAYE3 cascaded? Do I need one or two IDELAYCTRL? Any constraint?

Many thanks

S

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Re: IDELAYE3 and IDELAYCTRL

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Hi @scmicron

You should only need one IDELAYCTRL and no constraint. The IDELAYCTRL is per nibble and it controls all IDELAY and ODELAYS in the nibble.

If Vivado encounters something that stops the automatic replication of the IDELAYCTRL it will issue a error explaining that and you then can add the constraints if needed.

set_property IODELAY_GROUP MIXED_DELAY_GROUP_NAME [get_cells <<IDELAYCTRL instance name>>]
set_property IODELAY_GROUP MIXED_DELAY_GROUP_NAME [get_cells <<IDELAY and ODELAY instances name>>]

Sandy

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Participant scmicron
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Registered: ‎08-23-2017

Re: IDELAYE3 and IDELAYCTRL

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Hello @sandrao

I get error messages as follows: more of these are present, but I just report the very first.

[Place 30-803] Clock region X2Y1 has 4 IODELAY_GROUPs, either due to locked IO-Delay elements or due to locked IdelayCtrls. List of groups in this clock region:
Group "IODELAY_GROUP_RX_L0":
IdelayCtrl inst: design_1_i/.../RX_L0_DELAY_CTRL/IDELAYCTRL_0
Delay inst: design_1_i/.../RX0_inst/IDELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y143)
Delay inst: design_1_i/.../RX0_inst/ODELAYE3_inst (Locked to site BITSLICE_RX_TX_X0Y143)
...

In our design, there are 4 control blocks, each with an instance of an IDELAYCTRL and custom controller logic to update the IDELAYE3/ODELAYE3 instances (as per UG571 documentation). The ready signal of each IDELAYCTRL block goes into the controller logic who then presents a pulse over LOAD and DATA to the IDELAYE3/ODELAYE3 instances (remember: in TIME and VAR_LOAD mode).

I then used the following pair of constraints, one for each IDELAYCTRL:

set_property IODELAY_GROUP IODELAY_GROUP_RX_L0 [ get_cells design_1_i/.../RX_0/IDELAYCTRL_0 ]
set_property IODELAY_GROUP IODELAY_GROUP_RX_L0 [ get_cells { design_1_i/.../RX0_inst[i]/IDELAYE3_inst design_1_i/.../RX0_inst/ODELAYE3_inst } ]

The RX0_inst[i] in the second constraint goes from 0 to 25, since we have 25 bits there to delay.

How can I fix this?

Thanks

Best regards

S

 

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Re: IDELAYE3 and IDELAYCTRL

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Hi @scmicron

 

I find it useful when I'm building constraints to run them in the Vivado TCL console, to see what the results are. 

 

If you run this section of the constraint, what do you see? 

get_cells { design_1_i/.../RX0_inst[i]/IDELAYE3_inst design_1_i/.../RX0_inst/ODELAYE3_inst }

 

I suspect that the problem is that you are defining it as RX0_inst[i] but in the implemented design this is actually RX0_inst[0] upto RX0_inst[25]

If you run it with a wildcard does it report back all the instances 

get_cells { design_1_i/.../RX0_inst[*]/IDELAYE3_inst design_1_i/.../RX0_inst/ODELAYE3_inst }

 

then it would be 

set_property IODELAY_GROUP IODELAY_GROUP_RX_L0 [ get_cells { design_1_i/.../RX0_inst[*]/IDELAYE3_inst design_1_i/.../RX0_inst/ODELAYE3_inst } ]

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Participant scmicron
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Registered: ‎08-23-2017

Re: IDELAYE3 and IDELAYCTRL

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Hi @sandrao

Indeed I do use the Tcl console as well to check constraints.

And also, I am using the wildcard. I just copied and pasted the wrong line there. Sorry for that. The constraints are grouped in pairs as follows:

 

set_property IODELAY_GROUP IODELAY_GROUP_RX_L0 [ get_cells .../IDELAYCTRL_0 ]

set_property IODELAY_GROUP IODELAY_GROUP_RX_L0 [ get_cells { .../RX_Bus_idel[*].usPlusRxDelCasc_RX0_inst/IDELAYE3_inst .../RX_Bus_idel[*].usPlusRxDelCasc_RX0_inst/ODELAYE3_inst } ]

 

In the meanwhile, I have also tried to instantiate one single IDELAYCTRL and constraint it binding it with the different IDELAYE3/ODELAYE3 instances in the whole design. In this case, no error is given (but for a setup violation that is on my side of the design).

So, which is better then? One single IDELAYCTRL bound to the ~100 IDELAYE3/ODELAYE3 instances or 4 IDELAYCTRLs grouping ~25 IDELAYE3/OdELAYE3 each?

Many thanks

Cheers

S

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Community Manager
Community Manager
618 Views
Registered: ‎08-08-2007

Re: IDELAYE3 and IDELAYCTRL

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Which is better would depend on the System requirements. Either way the same amount of IDELAYCTRLs will be used in the design (one per nibble using at least one TIME mode delay element)

The approach of using one IDELAYCTRL and allowing Vivado to replicate is easier, however they you have one RDY signal that is all the RDY's AND'ed together. 

You need to follow the Reset Sequence and one of the steps is to wait for the RDY signal, so you will be waiting for all IDELAYCTRLs to be RDY.

If you have 4 Control Blocks then they may want it to be more granular, that each has its own RDY signal and can reset just that Control block. To do this you'd go back to the IDELAYCTRL within the Control Block and use the constraints. 

 

The error message says 

[Place 30-803] Clock region X2Y1 has 4 IODELAY_GROUPs

Meaning that the 4 Control Blocks are within the one clock region/bank, is that correct?

As long as the IOs in each Control Block don't try to share nibble that should be fine, you could try to LOC the 4 IDELAYCTRLs and see if that resolves the issue.

To check which nibble that IOs are, in the pin name there is the TxU or TxL

For example : IO_L22N_T3U_N7_DBC_AD0N_67 would be Byte 3 Upper Nibble. 

 

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