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Visitor jaklapel
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3,210 Views
Registered: ‎02-22-2017

MIO gem_tsu interface

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We are working on a new board design and were examining the MIO interface for the Zynq Ultrascale+ MPSoC when we came across the "gem_tsu" interface in the Technical Reference Manual (TRM).  We assume this has something to do with the Gigabit Ethernet Controller's Time Stamp Unit, but can't find any specific references in the TRM (or anywhere else online) that specifically mention what this interface is used for.  It's only 1 bit wide and we can venture guesses, but weren't sure.  Is there more documentation on this somewhere that we are missing?

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Teacher muzaffer
Teacher
5,826 Views
Registered: ‎03-31-2012

Re: MIO gem_tsu interface

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@jaklapel 

check out the zynq us+ register spec at https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

 

this shows: GEM_CLK_CTRL register tsu_clk_sel and also GEM_TSU_REF_CTRL register which shows how to get this clock generated.

 

TSU clock is basically the clock which samples all the time stamp values for all 4 gem blocks so that one can get reliable time-stamp information.

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Teacher muzaffer
Teacher
5,827 Views
Registered: ‎03-31-2012

Re: MIO gem_tsu interface

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@jaklapel 

check out the zynq us+ register spec at https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

 

this shows: GEM_CLK_CTRL register tsu_clk_sel and also GEM_TSU_REF_CTRL register which shows how to get this clock generated.

 

TSU clock is basically the clock which samples all the time stamp values for all 4 gem blocks so that one can get reliable time-stamp information.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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