01-28-2019 11:39 AM
I am using ISERDESE3 of "ULTRASCALE" for one of the IPs. However, when I change the "SIM_DEVICE" attribute to "ULTRASCALE_PLUS", the ISERDESE3 operation changes, failing my IP's operation.
Can someone point me to the changes that occur in ISERDESE3 when migrating from ULTRASCALE to ULTRASCALE_PLUS?
01-28-2019 12:12 PM - edited 01-28-2019 12:14 PM
This may help to point out all the differences... https://www.xilinx.com/support/documentation/data_sheets/ds890-ultrascale-overview.pdf
Also, depending on your chip... https://www.xilinx.com/support/documentation/user_guides/ug1213-zynq-migration-guide.pdf
But, I think the core difference is the manufacturing process was shrunk... 20 down to 16nm, which of course reflect better in power and performance.
Hope that helps
If so, please mark as solution accepted. Kudos also welcomed. :-)
01-28-2019 12:28 PM
01-30-2019 03:58 PM - edited 01-30-2019 04:00 PM
Thank you for sharing the links. I appreciate your time and efforts. However, unfortunately, none of the guides that you mentioned has the changes made in ISERDESE library component. From my empirical results, I can figure out that Ultrascale+ ISERDESE has more latency than Ultrascale. It is surprising to know that latency has increased, and even more surprising that Xilinx has not documented it anywhere.