11-27-2018 10:47 PM
My question is about initialization of RF ADC in ZCU111 board.
It is written in pg269 on page 32
"The IP core also handles the configuration and powerup of the data converters. This ensures that the settings specified in the Vivado IDE are applied to the RF-ADCs and RF-DACs immediately after the PL configuration completes."
When I open example design simulation,
1) It first writes simulation speed up registers.
2) write restart state register and restart power on state machine registers for all tiles.
3) Read "restart state registers" and "current state registers" for all tiles until they reach a specific state (powered up).
So these steps are fine as we waited for ADCs and DACs to power up. Then example design write all configuration data to ADCs and DAC tiles like mixer config, mixer mode etc.
My question is: In our custom design, should we just wait for power up (till point 3 above) and start reading ADC values? Or should we program all configuration data too?
If we follow the text in blue, What I get is, that IP will send all configuration data itself (according to what we programmed in IP config window). If that is true, in example design, where is this data going automatically to IP? All I see is config data is also sent to IP by testbench.
11-28-2018 10:19 PM
Is there anyone who can answer this query? or aren't there many people at xilinx who can answer queries on these advance devices?
@klumsde : You seem to answer queries on RFSOCs. Will you or someone else?
12-04-2018 09:30 AM
In hardware you get the IP config loaded with the bitfile, there is no need to intervene and change settings unless you need to.
The Example design has a folder called Imports
In here you will find
In here you can see it turning off the mixer and turning off Chopping in the ADC since the sim only makes a check that a triangle wave is increasing or decreasing in magnitude and having the mixer on makes no sense because the signal is real and not complex. Chopping won't make an appreciable difference to the output of the ADC and the only thing they will do is add run time.
If you are doing something more elaborate then you can go in and remove these writes so that you get the IP as is with the mixer enabled etc.
12-04-2018 10:51 PM
Thanks Keith (@klumsde ) for such a fast reply :S
I got it that in hardware, we dont need to program anything. Just we need to read current status register of ADCs until they are all giving value "2" ?
In simulation (and hardware), after power up (current state registers giving 2 on reading), do we need to just give data at analog inputs and it will come on AXI channels?
12-05-2018 08:04 AM
The end state of the tile is 0xF in the startup
After this you can consider the output on the ADC AXI stream valid.
12-06-2018 02:44 AM
I am reading for current state register for value 2 because in example design, When it reads 4 ADC tile current state registers as 2, it takes as configuration completed.
In custom design, upon your suggestion, I am reading values of current state registers of 4 ADC tiles in 4 registers to reach till value F but design is run for 420 us (in more than an hour) and still it is stuck on value 7 (which is clock configuration step). It is not reaching next state.
Do I need to run sim for long or am I doing something wrong that it's not moving forward?