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Explorer
Explorer
170 Views
Registered: ‎06-19-2014

RFSOC reference clock drift effect

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I am using zcu111 board and vivado 2018.1.

I want to generate reference frequencies for ADC PLL and AXI stream interface.

IP calculated ADC reference clock (and AXI stream clk) as 249.875 Mhz for one tile and 225.125 Mhz for another tile.

I am using clocking wizard to generate 249.875 MHz. Based on PLL input frequency, the closest achieved frequency 249.872 MHz. 

My question is, If I use this frequency, will this frequency difference ( 249.875 - 249.872 MHz ) make any effect on performance of ADC or AXI stream interface or is it fine?

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1 Solution

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Moderator
Moderator
143 Views
Registered: ‎04-18-2011

Re: RFSOC reference clock drift effect

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The Stream clock frequency is given by: 

PLDataRate = (ADCDataRate x 2GIQMode) / Decimation Factor

*** 2G IQ mode is 2 when you are using a 2GSPS ADC and IQ output data. Otherwise set it to 1. ******

AXI4-Stream Clock x PLNumWords = PLDataRate

AXI4-Stream Clock = PLDataRate / PLNumWords

You have to keep the data rate through the FIFO constant during operation. 

No frequency drift is allowed between the PL Clock domain and the Tile Clock domain. 

If there is a frequency mismatch you risk overflowing the FIFO. 

 

 

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2 Replies
Community Manager
Community Manager
155 Views
Registered: ‎08-30-2011

回复: RFSOC reference clock drift effect

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@a4speaker

I recommend to use clock output from the IP and it won't be a problem for your case any longer.

You can find the clock output the frequency you set accordingly from the IP module.

image.png

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Moderator
Moderator
144 Views
Registered: ‎04-18-2011

Re: RFSOC reference clock drift effect

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The Stream clock frequency is given by: 

PLDataRate = (ADCDataRate x 2GIQMode) / Decimation Factor

*** 2G IQ mode is 2 when you are using a 2GSPS ADC and IQ output data. Otherwise set it to 1. ******

AXI4-Stream Clock x PLNumWords = PLDataRate

AXI4-Stream Clock = PLDataRate / PLNumWords

You have to keep the data rate through the FIFO constant during operation. 

No frequency drift is allowed between the PL Clock domain and the Tile Clock domain. 

If there is a frequency mismatch you risk overflowing the FIFO. 

 

 

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------