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Ultra scale JTAG TDO pin, is it Open collector ?

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Scholar
Posts: 1,733
Registered: ‎07-09-2009
Accepted Solution

Ultra scale JTAG TDO pin, is it Open collector ?

I look at the TDO pin of the FPGA with a scope whilst using the sysmon to measure temperature,

 

FPGA is un configured.

 

most of the time, TDO look's like a nice square edged waveform,

     

but

   

Every second or so, I see a slow rising edge, as one would have with an Open collector , with a rise time of the order of 1 us.

 

Checked other pins, and all good square edges, checked psu, all good.

 

 

IMG_20170519_102002.jpg

Accepted Solutions
Xilinx Employee
Posts: 168
Registered: ‎08-08-2007

Re: Ultra scale JTAG TDO pin, is it Open collector ?

Looking at UG570 Table 6-1: TAP Controller Pins it says :
TDO Out Pull-up Test Data Out - TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device. TDO is an active driver output. TDO has an internal resistive pull-up to provide a logic High if the pin is not active.

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Xilinx Employee
Posts: 168
Registered: ‎08-08-2007

Re: Ultra scale JTAG TDO pin, is it Open collector ?

Looking at UG570 Table 6-1: TAP Controller Pins it says :
TDO Out Pull-up Test Data Out - TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device. TDO is an active driver output. TDO has an internal resistive pull-up to provide a logic High if the pin is not active.