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253 Views
Registered: ‎07-11-2018

Ultrascale+ XCZU Power Up Sequence

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For the power up / power down sequence, what happens if I have a 3.3V IO voltage present on the PL side HD banks before the other VCCINT, VCCINT_IO/VCCBRAM/VCCINT_VCU, VCCAUX/VCCAUX_IO rails are turned on?

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Moderator
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209 Views
Registered: ‎09-18-2014

Re: Ultrascale+ XCZU Power Up Sequence

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I meant forum posts not necessarily xilinx articles. The same thing applies to all Xilinx devices in that the recommended sequence guarantees minimum current draw and expected IO tristate behavior. If you don't follow the recommended sequence all bets are off and those guarantees no longer apply. There are too many supplies and supply sequencing combinations to characterize them all. We don't have specifics that I know of. Since the device quality is not affected by non recommended sequencing you may test/characterize this on your own. One thing that has usually been consistent over the generations is that to reduce majority of the current and get expected IO behavior is to generally follow VCCINT>VCCAUX>VCCO. 

 

Regards,

Tezz

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Moderator
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235 Views
Registered: ‎09-18-2014

Re: Ultrascale+ XCZU Power Up Sequence

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Hi Patryk.laslowski,

 

There are multiple forum posts regarding this topic but to get to the point as the data sheet states if you don't follow the recommended sequence then neither minimum current draw nor tristate IO behavior can be expected. If your design can tolerate higher power up current and device IOs glitching/not-tristate during power up then you are free to do so. 

 

Regards,

Tezz

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233 Views
Registered: ‎07-11-2018

Re: Ultrascale+ XCZU Power Up Sequence

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Hi Tezz,

I've tried to find articles on this but nothing specific to Ultrascale+. Am I missing something?

 

Is there any info as to what these higher currents look like and what type of glitches / non-tristate behaviour to expect? 

 

Thanks,

Patryk

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Moderator
Moderator
210 Views
Registered: ‎09-18-2014

Re: Ultrascale+ XCZU Power Up Sequence

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I meant forum posts not necessarily xilinx articles. The same thing applies to all Xilinx devices in that the recommended sequence guarantees minimum current draw and expected IO tristate behavior. If you don't follow the recommended sequence all bets are off and those guarantees no longer apply. There are too many supplies and supply sequencing combinations to characterize them all. We don't have specifics that I know of. Since the device quality is not affected by non recommended sequencing you may test/characterize this on your own. One thing that has usually been consistent over the generations is that to reduce majority of the current and get expected IO behavior is to generally follow VCCINT>VCCAUX>VCCO. 

 

Regards,

Tezz

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204 Views
Registered: ‎07-11-2018

Re: Ultrascale+ XCZU Power Up Sequence

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Thanks for the feedback.

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