09-03-2017 05:31 AM
We are designing a project with ZYNC Ultrascale+, zu19e1924, using also the CPRI LogiCore in the project.
I have a few questions which I’ll be happy to discuss about, especially about the clocking and the abilities to change them on the fly.
Also, about the Transceivers (We want to be set to 24G, 12G etc.).
Our design intends to use 36 units of CPRI LogiCore in this project.
Do I need to consider an MMCM unit for each CPRI unit in this project?
May I use a single MMCM for 7 units? I saw in the data sheets that a single MMCM unit can split 7 clocks. But, how can it be changed? Can it be configured on the fly? Or just once before synthesis?.
In the pg056-cpri_v87.pdf, p.161 it's written that in Ultrascale+ devices, there is no use of MMCM in the clocking. So, who pushes the clock? If I need to change the input clock, to produce it in other rates, how can it be done?
From where do I need to support the clk_in to the transceiver \ CPRI LogiCore?
Also, about the support layer - which can be instantiated in the CPRI LogiCore settings - How can I connect and share the support layer for multiple CPRI LogiCores? In continue to the former questions, if the CPRI LogiCores unit use different clocks (rates), how can it be done?
Thank you very much in advance,
09-03-2017 11:32 PM
Yes, it was a mistake. I found that the first post had been placed in the wrong discussion. I didn't find how to delete it.