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Registered: ‎02-06-2019

Zynq MPSoC power supply

Hello all


We are about to use Zynq MPSoC in our board. Also, it contains other FPGA's & Processor. So, the board is getting densed and we decided to reduce the  no.of power modules required for Zynq. 


As per UG583 we decided to follow "Always On: Cost-Optimized Power Rail Consolidation" as shown in below pic.

ps ultrascale.png


now the question is

1. Do we need to take any precautions in design point of view.


Also mentioned in UG583, the required de-cap's for different power rails separately for PL & PS rails for a "25% STEP LOAD". But we're combining PL internal supply & PS LPD,FPD supplies here.

2. Do we still need to place the suggested de-cap's for rails. (source is one module for all)

3. what about this "step load"? how to calculate?


thank you..

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