UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor veekshitha
Visitor
132 Views
Registered: ‎08-13-2019

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk] why is this constraint used?

Jump to solution

I used zynq ultrascale  xczu5ev-fbvb900-1-i SoC for tuning of transceiver.It showed the followig error

[DRC PLHDIO-4] HDIO DRC Checks: The following IO terminals are locked to HIGH_DENSITY IO banks, but they drive a PLL/MMCM/BUFGCTRL/BUFGCE_DIV instance which cannot be placed in HIGH_DENSITY banks due to absence of such sites. Please review and update the LOC constraints:
gth_sysclkp_i

So, i added  RTL INSTANTIATION in the example design file(.v file)

assign gth_sysclk_i = gth_sysclkp_i;
BUFGCE #(
.CE_TYPE("SYNC"), // ASYNC, HARDSYNC, SYNC
.IS_CE_INVERTED(1'b0), // Programmable inversion on CE
.IS_I_INVERTED(1'b0) // Programmable inversion on I
)
BUFGCE_inst (
.O(temp_clk), // 1-bit output: Buffer
.CE(1'b1), // 1-bit input: Buffer enable
.I(gth_sysclkp_i) // 1-bit input: Buffer
);

It showed the following error once i added buffer.

[Place 30-716] Sub-optimal placement for a global clock-capable IO pin-BUFGCE-MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk] >

BUFGCE_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_HDIO_X1Y5
dbg_hub/inst/BSCANID.u_xsdbm_id/USE_DIVIDER.ULTRASCALEPLUS.U_GT_MMCM (MMCME4_ADV.CLKIN1) is provisionally placed by clockplacer on MMCM_X0Y3

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
BUFGCE_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_HDIO_X1Y5

Clock Rule: rule_gclkio_bufg
Status: PASS
Rule Description: An IOB driving a BUFG must use a GCIO in the same clock region as the BUFG
gth_sysclkp_i_IBUF_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y112
BUFGCE_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_HDIO_X1Y5

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
BUFG
dbg_hub/inst/BSCANID.u_xsdbm_id/USE_DIVIDER.ULTRASCALEPLUS.U_GT_MMCM (MMCME4_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCM_X0Y3
dbg_hub/inst/BSCANID.u_xsdbm_id/USE_DIVIDER.BUFG_inst_div (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y82

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
and dbg_hub/inst/BSCANID.u_xsdbm_id/USE_DIVIDER.BUFG_inst_div (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y82

I added the  clock constraint in .xdc file 

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk]

once I made the above changes it worked fine .

but my question is ,

1)why is the clock constraint required for xczu5ev?why does it show error without the clock constraint?

2)for the xczu7ev there was no necessity  of giving the above clock constraint .It worked fine without the constraint .Why is it so?

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
77 Views
Registered: ‎08-08-2017

Re: set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk] why is this constraint used?

Jump to solution

Hi @veekshitha 

Looking at the below DRC

[DRC PLHDIO-4] HDIO DRC Checks: The following IO terminals are locked to HIGH_DENSITY IO banks, but they drive a PLL/MMCM/BUFGCTRL/BUFGCE_DIV instance which cannot be placed in HIGH_DENSITY banks due to absence of such sites. Please review and update the LOC constraints: gth_sysclkp_i.  

It seems you have using HDGC pin to bring the clock onto the device . 

HD I/O banks do not have  CMT next to them, the HDGC pins can only directly drive BUFGCEs (BUFGs) and not
MMCMs/PLLs. Therefore, clocks that are connected to an HDGC pin can only connect to MMCMs/PLLs through the BUFGCEs. To avoid a design rule check (DRC) error, set the property CLOCK_DEDICATED_ROUTE = FALSE.

Any CMT COLUMN is used in below case

When driving from a clock buffer to other clock regions that are not vertically adjacent, you must set the CLOCK_DEDICATED_ROUTE  to ANY_CMT_COLUMN for UltraScale devices. This prevents implementation errors and ensures that the clock is routed with global clock resources only

Capture.PNG

Can you please share your project archive or clocking schematic to gain the better ubderstanding of your clock connections?

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
6 Replies
Explorer
Explorer
117 Views
Registered: ‎12-05-2016

Re: set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk] why is this constraint used?

Jump to solution

 

Hi @veekshitha,

Please refer clocking guidelines(page 89-91) in  https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug949-vivado-design-methodology.pdf 

It will give an idea about the usage of these constaraints.

To comment on the second question, Could you please give the complete part number of FPGAs (xczu5ev & xczu7ev) used? 

Regards,

Reshma 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Visitor veekshitha
Visitor
108 Views
Registered: ‎08-13-2019

Re: set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk] why is this constraint used?

Jump to solution

Hi @reshmaakhil 

Will go through the document suggested .

I use xczu5ev-fbvb900-i and xczu7ev-fbvb900i.

Thank you,

Regards

 

0 Kudos
Moderator
Moderator
78 Views
Registered: ‎08-08-2017

Re: set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk] why is this constraint used?

Jump to solution

Hi @veekshitha 

Looking at the below DRC

[DRC PLHDIO-4] HDIO DRC Checks: The following IO terminals are locked to HIGH_DENSITY IO banks, but they drive a PLL/MMCM/BUFGCTRL/BUFGCE_DIV instance which cannot be placed in HIGH_DENSITY banks due to absence of such sites. Please review and update the LOC constraints: gth_sysclkp_i.  

It seems you have using HDGC pin to bring the clock onto the device . 

HD I/O banks do not have  CMT next to them, the HDGC pins can only directly drive BUFGCEs (BUFGs) and not
MMCMs/PLLs. Therefore, clocks that are connected to an HDGC pin can only connect to MMCMs/PLLs through the BUFGCEs. To avoid a design rule check (DRC) error, set the property CLOCK_DEDICATED_ROUTE = FALSE.

Any CMT COLUMN is used in below case

When driving from a clock buffer to other clock regions that are not vertically adjacent, you must set the CLOCK_DEDICATED_ROUTE  to ANY_CMT_COLUMN for UltraScale devices. This prevents implementation errors and ensures that the clock is routed with global clock resources only

Capture.PNG

Can you please share your project archive or clocking schematic to gain the better ubderstanding of your clock connections?

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
Visitor veekshitha
Visitor
59 Views
Registered: ‎08-13-2019

Re: set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk] why is this constraint used?

Jump to solution

Hi @pthakare 

Thank you so much for the reply .

Regards,

Veekshitha

0 Kudos
Visitor veekshitha
Visitor
57 Views
Registered: ‎08-13-2019

Re: set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk] why is this constraint used?

Jump to solution

Hi @pthakare 

My doubt is Why doesnt 7ev require that clock constraint ? Is the clock region vertically adjacent in xczu7ev-fbvb9000-i?

Regards,

Veekshitha

0 Kudos
Moderator
Moderator
13 Views
Registered: ‎08-08-2017

Re: set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets temp_clk] why is this constraint used?

Jump to solution

Hi @veekshitha 

Can you please send us your project archive to further invistagation on this. At this stage we are not clear with clocking scheme in your design.

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos