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Adventurer
Adventurer
674 Views
Registered: ‎01-10-2011

two separate clocks for ISERDES in Kintex Ultrascale

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UG571 in the chapter on Serdes Clocking considerations (pp194) seems to indicate that the slow clock be derived from the high-speed clock with either an MMCM/PLL or BUFGCE_DIV. In my board, I already have separate clocks for the high-speed and low speed clocks at the correct frequency relation (4:1) for a DDR 8bit deserialization. Can these clocks be used instead of deriving the slow clock as described in UG571?

Jo

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Historian
Historian
668 Views
Registered: ‎01-23-2009

Re: two separate clocks for ISERDES in Kintex Ultrascale

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So what you say is not technically correct. The "legal" configurations are

  - both the slow and fast clocks come from different outputs of the same MMCM

  - the fast clock comes a BUFGCE and the slow clock from a BUFGCE_DIV with the proper divider

    - the inputs of the BUFGCE and BUFGCE_DIV must be the same high speed clock

 

If your two clocks conform to one of these two architectures, then it may be OK to use them. If they are anything else then you cannot.

 

Even with the "legal" clocking structures, people are having trouble meeting the skew requirement between the two clocks - you can take a look at this post on managing the skew to the OSERDES (the ISERDES should have the same issues).

 

Avrum

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4 Replies
Historian
Historian
669 Views
Registered: ‎01-23-2009

Re: two separate clocks for ISERDES in Kintex Ultrascale

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So what you say is not technically correct. The "legal" configurations are

  - both the slow and fast clocks come from different outputs of the same MMCM

  - the fast clock comes a BUFGCE and the slow clock from a BUFGCE_DIV with the proper divider

    - the inputs of the BUFGCE and BUFGCE_DIV must be the same high speed clock

 

If your two clocks conform to one of these two architectures, then it may be OK to use them. If they are anything else then you cannot.

 

Even with the "legal" clocking structures, people are having trouble meeting the skew requirement between the two clocks - you can take a look at this post on managing the skew to the OSERDES (the ISERDES should have the same issues).

 

Avrum

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Adventurer
Adventurer
660 Views
Registered: ‎01-10-2011

Re: two separate clocks for ISERDES in Kintex Ultrascale

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I might have said it incorrectly, but that's exactly what I was trying to say. So what you are saying is that having two different clock pins (clock capable I/Os) even with the correct frequency ratio and a fixed phase between them is not a "legal" configuration?

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Adventurer
Adventurer
656 Views
Registered: ‎01-10-2011

Re: two separate clocks for ISERDES in Kintex Ultrascale

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I probably should have expanded even more:

So what you are saying is that having two different clock pins (clock capable I/Os) even with the correct frequency ratio and a fixed phase between them (and both going to their own BUFGCE) is not a "legal" configuration?

The reason that I am asking this is that the data source for the serialized data is an external chip that provides the data, the high-speed clock and the low speed clock (both programmable in freq and phase), so in essence does what the "legal" configuration does inside the FPGA instead. It would be have been nice to somehow use those clocks rather than dividing the clock inside the FPGA again.

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Historian
Historian
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Registered: ‎01-23-2009

Re: two separate clocks for ISERDES in Kintex Ultrascale

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So what you are saying is that having two different clock pins (clock capable I/Os) even with the correct frequency ratio and a fixed phase between them (and both going to their own BUFGCE) is not a "legal" configuration?

 

No, this is not legal. The legal clocking schemes are described in the SelectIO User Guides (UG571 for US/US+), in the section "Clocking Considerations Using Component Primitives". (v1.9, p.194). The scheme you described is not shown there, so is not legal.

 

In addition, US/US+ has very strict skew requirements on these two clocks (that are checked by the tool) - even using the legal clocking techniques and the required attributes (CLOCK_DELAY_GROUP) it doesn't always work.

 

Generally when a device (often an ADC) provides a source synchronous bit clock and "frame clock", the "frame clock" is not used as a clock by the FPGA - it is used as data; sampled at the same rate (and phase) as the data, and used to detect the proper framing pattern (with the 0->1 transition on the first bit of the framed word). Take a look at this post on recovering framing from a high speed serial (or serialized) link.

 

Avrum

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