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83 Views
Registered: ‎08-14-2019

uhdsdi_gt_wrapper/GTSOUTHREFCLK1_CLK/U0/IBUF_OUT[0] is not completely routed.

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I use the FPGA part xczu4ev Mercury Enclustra board. And I try to use example IP design for the uhdsdi - gt and RX (receiver) system. I have the following error when I run implementation:

[Route 35-54] Net: i_design_1/design_1_i/uhdsdi_gt_wrapper/GTSOUTHREFCLK1_CLK/U0/IBUF_OUT[0] is not completely routed.

What can be the possible solution? How to debug it?

Unbenannt1.PNG
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Moderator
Moderator
37 Views
Registered: ‎07-30-2007

Re: uhdsdi_gt_wrapper/GTSOUTHREFCLK1_CLK/U0/IBUF_OUT[0] is not completely routed.

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I see on this chip there is only one quad.  It is not possible to use the north/south refclk inputs.  You have a refclk from the quad you're in trying to drive a southrefclk port. 

Drive gtrefck1 with the SI5324 input as it is now and drive gtrefclk0 with the SI570 input.

On the GT common the SI570 should drive GTREFCLK00 and GTREFCLK01.

 

Roy


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3 Replies
Moderator
Moderator
54 Views
Registered: ‎07-30-2007

Re: uhdsdi_gt_wrapper/GTSOUTHREFCLK1_CLK/U0/IBUF_OUT[0] is not completely routed.

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Can't say for sure what the problem is with just this information.  To use the reference clock pins to drive a recovered clock off the chip use the OBUFDS_GTE4 primitive.  It looks like you may have tried to do this with something else.  Similarly the refclk input would drive the GT  southrefclk through a IBUFDS_GTE4 primitive.  If there is only one refclk input and you will not be dynamically changing refclk's you would drive the gtrefclk0 pin and set the *refclksel to 001.  Vivado will take care of the rest.  Also these are all things normally taken care of in the example design.  Are you using the example design?

Roy


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Don't forget to reply, kudo, and accept as solution
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43 Views
Registered: ‎08-14-2019

Re: uhdsdi_gt_wrapper/GTSOUTHREFCLK1_CLK/U0/IBUF_OUT[0] is not completely routed.

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I am using the example design. While importing the design, some parts of the FPGA board did not match, and after completing the Report_ip_status, when I run implementation, this error appears. Also, I am using Vivado 2018.2

Please find the dcp file

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Moderator
Moderator
38 Views
Registered: ‎07-30-2007

Re: uhdsdi_gt_wrapper/GTSOUTHREFCLK1_CLK/U0/IBUF_OUT[0] is not completely routed.

Jump to solution

I see on this chip there is only one quad.  It is not possible to use the north/south refclk inputs.  You have a refclk from the quad you're in trying to drive a southrefclk port. 

Drive gtrefck1 with the SI5324 input as it is now and drive gtrefclk0 with the SI570 input.

On the GT common the SI570 should drive GTREFCLK00 and GTREFCLK01.

 

Roy


----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------