07-03-2018 06:39 AM
I am trying to connect a time-to-digital conversion device (ams TDC-GPX2) to the FPGA using the SERDES/LVDS interface. The problem is that the SelectIO component provides a maximum serialization factor of 14 at DDR, but the device provides 44 bit serialization.
Is it possible to connect multiple SelectIO to work around the issue?
I have tried also the deserialization core in XAPP1107, but it doesn't seem to work properly, even using smaller serialization factors.
Does anyone have an hint? Thank you
07-09-2018 03:10 PM
Are you using the FPGA to drive the input to the GPX2? Or read the output from it? I can't see anything about 44-bit serialization on either interface.
For driving the input, you should be fine to use a serialization factor of 2 or 4 in the hardware (reducing the on-chip clock speed to 100MHz or 50MHz, both of which are easily achievable with any modern FPGA).
For reading the output, the clock speed is only 40MHz - you can just wire that up to a shift register (no SERDES required) to get the data.
07-14-2018 05:32 AM
You are probably referring to the TDC-GPX1. The GPX2 has 4 differential outputs with LVDS and with encoder serialized from 14 to 44 bits.
I am using the interface to both drive it, but that is done using the SPI port, and reading the output of 2 of 4 encoders.