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ParhamZR
Observer
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Registered: ‎01-14-2021

AXI DMA / interconnect maximum frequency of operation

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Hello, 
I am using the ZCU111 board and am fairly new to the world of FPGA. My plan is to get a stream of real data from ADC tile 228 at 4.096 GHz (4 GSPS) and get it out from the ethernet at this point. Attached is an screen shot of my design in Vivado. The purple wire is 250 MHz PL fabric clock that run the peripheral by arm core and control flow. The green wire is clk_adc0 (256 MHz), out put clock of ADC and the red wire is output clock of clocking wizard (512 MHz) which is the clock for data flow. The Cyan color is the reset signals for clocking wizard and 3 processor system resets (I am not sure if this the correct configuration for reset signals so I asked that question here: https://forums.xilinx.com/t5/Versal-and-UltraScale/Reset-pins-for-the-clocking-wizard-system-process-reset-in/m-p/1259716). 

ADC samples at 4.096 GHz and creates 16bits of data at the each clock cycle. The output flow of ADC (I call this ADC sample for the rest of this question) is 128 bits of data at 512 MHz. ADC samples goes to DMA engine where after 16 ADC sample a TLAST signal is generated. this is matched with the width of buffer length register which is 8. After 16 clock cycle, @512MHz, the length register is full, tlast is generated and transfer begins. (256 Bytes of data) . The screen shot of DMA configuration is attached. As the S-AXI HP0 FPD cannot operates at frequency no more than 333 MHz, I connect the port to frequency of 256MHz. DMA engine connects to S-AXI-HPO-FPD port through an AXI interconnect which works at 2 different frequencies with ratio of 2:1. (According to PG059 page108)



Here are my questions (detailed block diagram screenshot is provided): 
1- The input stream is 128 bit wide at clock frequency of 512MHz (DMA S2MM frequency), the output memory mapped data out of interconnect is 128 bit at 256MHz, and the width of data is neither changed in the DMA nor in the interconnect. How can DMA transfer the data and meet the timing ? shouldn't be a data overflow ? or the length of memory mapped data be 256 bits ? 

2- When I run the implementation for this design, there is no negative WNS or WHS. Does that mean that DMA + Interconnect is going to keep up with the data flow ? 

3- If this configuration is fine,  how interconnect can transfer the data without falling behind ?
I read the manual but didn't find anything that answer my questions. 

Thank you in advance for your time and considerations. 

Tags (3)
dma_config.PNG
Design1.PNG
DMA_interconnect_PS_DDR.PNG
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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@ParhamZR ,

> 1. How can DMA transfer the data and meet the timing ? shouldn't be a data overflow ? or the length of memory mapped data be 256 bits ?

When the tools say that the DMA will meet timing at 256MHz, they mean that every flip-flop in the design will have its set up and hold requirements met.  That doesn't mean that it can keep up with your data rate, just that the setup and hold requirements are met.

If the data coming in is at 512MHz and 128 bits wide, then a DMA running at 256MHz and 128 bits wide will obviously not keep up.

2. When I run the implementation for this design, there is no negative WNS or WHS. Does that mean that DMA + Interconnect is going to keep up with the data flow ?

No.  It just means there's no negative slack.  The design meets timing, but it won't be able to handle your throughput.  That's not what "meets timing" means.

3- If this configuration is fine, how interconnect can transfer the data without falling behind

It can't keep up.

 

One of my criticisms of the AXI Stream protocol is that not all data streams can handle back pressure.  Let me assume for the moment that you are using AXI stream (I struggle to read pictures, and you haven't said it explicitly, but this is likely).  AXI Stream has the ability to put back pressure on the source data.  By dropping TREADY at appropropriate times, the ultimate slave can control the maximum data rate through the channel.  When you go from 512MHz down to 256MHz, that will force TREADY to be true (roughly) every other clock cycle.  (Reality is that it won't be exact--there will be bunched up cycles both where data is accepted and where it is not.--but it should average out to 50%).  The memory source will force it to be true even less often than that.  Your A/D data source can't handle that, but the protocol believes it can.  Indeed, most A/D data sources can't handle arbitrary back pressure.  You'll get an overflow through your pipeline.  It's roughly the same as if you were trying to drive a D/A and didn't generate the data fast enough.  In that case, you'd get an underflow, but the design would still meet timing.

My point is, this is one of the known but unwritten limitations of the AXI stream protocol: there's no way of expressing or handling throughput constraints like this in the protocol.  The design engineer has to work them out on his own in order to make sure they'll all be met.  Indeed, that's why you are getting paid the big bucks--right?

Dan

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dgisselq
Scholar
Scholar
457 Views
Registered: ‎05-21-2015

@ParhamZR ,

> 1. How can DMA transfer the data and meet the timing ? shouldn't be a data overflow ? or the length of memory mapped data be 256 bits ?

When the tools say that the DMA will meet timing at 256MHz, they mean that every flip-flop in the design will have its set up and hold requirements met.  That doesn't mean that it can keep up with your data rate, just that the setup and hold requirements are met.

If the data coming in is at 512MHz and 128 bits wide, then a DMA running at 256MHz and 128 bits wide will obviously not keep up.

2. When I run the implementation for this design, there is no negative WNS or WHS. Does that mean that DMA + Interconnect is going to keep up with the data flow ?

No.  It just means there's no negative slack.  The design meets timing, but it won't be able to handle your throughput.  That's not what "meets timing" means.

3- If this configuration is fine, how interconnect can transfer the data without falling behind

It can't keep up.

 

One of my criticisms of the AXI Stream protocol is that not all data streams can handle back pressure.  Let me assume for the moment that you are using AXI stream (I struggle to read pictures, and you haven't said it explicitly, but this is likely).  AXI Stream has the ability to put back pressure on the source data.  By dropping TREADY at appropropriate times, the ultimate slave can control the maximum data rate through the channel.  When you go from 512MHz down to 256MHz, that will force TREADY to be true (roughly) every other clock cycle.  (Reality is that it won't be exact--there will be bunched up cycles both where data is accepted and where it is not.--but it should average out to 50%).  The memory source will force it to be true even less often than that.  Your A/D data source can't handle that, but the protocol believes it can.  Indeed, most A/D data sources can't handle arbitrary back pressure.  You'll get an overflow through your pipeline.  It's roughly the same as if you were trying to drive a D/A and didn't generate the data fast enough.  In that case, you'd get an underflow, but the design would still meet timing.

My point is, this is one of the known but unwritten limitations of the AXI stream protocol: there's no way of expressing or handling throughput constraints like this in the protocol.  The design engineer has to work them out on his own in order to make sure they'll all be met.  Indeed, that's why you are getting paid the big bucks--right?

Dan

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