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Visitor zjywindwalk
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1,032 Views
Registered: ‎12-29-2018

Are there BUFIO like cells in ultrascale?

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I am working on timing closure of DDR IO, on utralscale FPGA.

And I got one solution from the the following link:

https://forums.xilinx.com/t5/7-Series-FPGAs/LVDS-DDR-input-constrains/m-p/694350#M16385

But in ultrascale, there is no BUFIO, which is recommended to achieve small data eye in the above solution.

So, are there BUFIO like cells in ultrascale?

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Historian
Historian
991 Views
Registered: ‎01-23-2009

Re: Are there BUFIO like cells in ultrascale?

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Yes and no.

In UltraScale/UltraScale+ the whole concept of clocking has been changed. The primary difference between the different buffers in the 7 series were the size of the dedicated clock net they drove:

  • A BUFG drove a clock network that spanned the entire device
  • A BUFR drove a clock network that spanned only one clock region
  • A BUFIO drove a clock network that only spanned the clocked cells in the I/O column of one bank

The smaller a clock network, the shorter the insertion delay. The fact that the BUFIO spanned only a small number of cells made the clock insertion very small, which led to little PVT variation to smaller capture windows. However, that being said, the BUFR timing for I/O is really pretty similar to the BUFIO - in fact, architecturally, I suspect they have a lot in common.

In UltraScale there are several different types of "global" clock buffers - BUFGCTRL, BUFGCE, BUFGCE_DIV - but they differ in functionality, not what they drive - they all drive the "global" clock network. I use the word "global" in quotes, since, while in the 7 series all global clock networks were truly global, in the US/US+, they are more flexible; the clock networks are built dynamically by the tool using the clock distribution and clock routing networks, and can end up with a clock network that spans as little as one clock region (which are smaller and more numerous in US/US+) to as large as the entire device (truly global).

So, with a "global" clock network that spans only one clock region (which is smaller than the clock region of the 7 series), the behavior of this clock would be similar to (or even better than) a BUFR in the 7 series.

So the trick to "BUFR-like" I/O performance is to have the clock come in on a clock capable pin, then go to a BUFGCE (or other global buffer), but restrict the clock to only one clock region. This can be done in a variety of manners, but I believe (I am not an expert in US/US+) the property "CLOCK_LOW_FANOUT" indicates to the tool that this is what you want. You need to place this property on the net driven by the BUFGE (the clock net) - this can be done either in the RTL using an attribute or in the XDC file.

Avrum

7 Replies
Historian
Historian
992 Views
Registered: ‎01-23-2009

Re: Are there BUFIO like cells in ultrascale?

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Yes and no.

In UltraScale/UltraScale+ the whole concept of clocking has been changed. The primary difference between the different buffers in the 7 series were the size of the dedicated clock net they drove:

  • A BUFG drove a clock network that spanned the entire device
  • A BUFR drove a clock network that spanned only one clock region
  • A BUFIO drove a clock network that only spanned the clocked cells in the I/O column of one bank

The smaller a clock network, the shorter the insertion delay. The fact that the BUFIO spanned only a small number of cells made the clock insertion very small, which led to little PVT variation to smaller capture windows. However, that being said, the BUFR timing for I/O is really pretty similar to the BUFIO - in fact, architecturally, I suspect they have a lot in common.

In UltraScale there are several different types of "global" clock buffers - BUFGCTRL, BUFGCE, BUFGCE_DIV - but they differ in functionality, not what they drive - they all drive the "global" clock network. I use the word "global" in quotes, since, while in the 7 series all global clock networks were truly global, in the US/US+, they are more flexible; the clock networks are built dynamically by the tool using the clock distribution and clock routing networks, and can end up with a clock network that spans as little as one clock region (which are smaller and more numerous in US/US+) to as large as the entire device (truly global).

So, with a "global" clock network that spans only one clock region (which is smaller than the clock region of the 7 series), the behavior of this clock would be similar to (or even better than) a BUFR in the 7 series.

So the trick to "BUFR-like" I/O performance is to have the clock come in on a clock capable pin, then go to a BUFGCE (or other global buffer), but restrict the clock to only one clock region. This can be done in a variety of manners, but I believe (I am not an expert in US/US+) the property "CLOCK_LOW_FANOUT" indicates to the tool that this is what you want. You need to place this property on the net driven by the BUFGE (the clock net) - this can be done either in the RTL using an attribute or in the XDC file.

Avrum

Visitor zjywindwalk
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942 Views
Registered: ‎12-29-2018

Re: Are there BUFIO like cells in ultrascale?

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Avrum,

Thank you very much for your reply, it is helpful. One more question to confirm.

In my project, data is latched by IDDR using strobe as clock. 

So I connect the strobe to DBC pins, and then place the "CLOCK_LOW_FANOUT" property on the net driven by the BUFGE, connected to the iob of strobe.

Am I right?

 

Thanks,

Jevon

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Scholar brimdavis
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Registered: ‎04-26-2012

Re: Are there BUFIO like cells in ultrascale?

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@zjywindwalk  "So, are there BUFIO like cells in ultrascale?"

Here are some older posts regarding constraining Ultrascale I/O clock trees that might be helpful:

    https://forums.xilinx.com/t5/UltraScale-Architecture/Trouble-Implementing-a-Simple-Source-Sync-Input-DDR-Interface/m-p/897828#M7493

    https://forums.xilinx.com/t5/Timing-Analysis/implementation-helps-FPGA-I-O-pass-STA/m-p/757816#M11358

    https://forums.xilinx.com/t5/UltraScale-Architecture/Zynq-Ultrascale-LVDS-in-native-mode/m-p/826945#M5927

Summary:

  •  forcing Ultrascale direct I/O clock trees into a single clock region produces better/more repeatable results
    • 2017.3 and later support CLOCK_LOW_FANOUT  (UG949 page 101)
    • earlier versions require USER_CLOCK_ROOT and PBLOCKs
  • the DBC/QBC clock pins work for "native mode" I/O, GC clock pins work for "component mode" I/O
    • only the GC_QBC pins work as clock sources in both native and component mode
  • XAPP1324 is a good reference for component mode I/O

-Brian

Historian
Historian
897 Views
Registered: ‎01-23-2009

Re: Are there BUFIO like cells in ultrascale?

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So I connect the strobe to DBC pins...

As @brimdavis mentioned, the DBC are for the "native mode" clocking - I have never used it, nor do I know how. If you want to use "BUFIO/BUFR-like" clocking, then you are working in "component mode" and the clock needs to be on a GC (not a DBC) pin, and connected through a BUFGCE to a clock net with CLOCK_LOW_FANOUT (and all logic driven by this clock must fit within one clock region).

Avrum

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Visitor zjywindwalk
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Registered: ‎12-29-2018

Re: Are there BUFIO like cells in ultrascale?

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Avrum,

Thank you. Must I insert a common cell, such as MMCM between the GC pin and the bufg?

In ug912, the syntax is

"XDC Syntax
set_property CLOCK_LOW_FANOUT TRUE [get_nets <clk_nets>]
Where
• <clk_nets> is a list of clock nets directly connected to the output of global clock
buffers, that are driven by a common cell, such as an MMCM for example.

"

But what I connected to the GC pin is a strobe, I don't want to insert a MMCM, instead I want to connect bufgce to iob directly. Is that OK?

 

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Visitor zjywindwalk
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Registered: ‎12-29-2018

Re: Are there BUFIO like cells in ultrascale?

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The stobe is used as non-continous clock and it is bidirectional。

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Historian
Historian
826 Views
Registered: ‎01-23-2009

Re: Are there BUFIO like cells in ultrascale?

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But what I connected to the GC pin is a strobe, I don't want to insert a MMCM, instead I want to connect bufgce to iob directly. Is that OK?

As far as I know, yes, it should be OK.

Avrum

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