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Visitor
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Registered: ‎12-17-2009

BUFGCE_DIV inverted I input

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On p31 of the Ultrascale Architecture Clocking Resources guide, v1.8 (dec'18) https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf, it states in a table that the I input pin of the buffer is not invertible.  Ie. you can't invert a clock thru it.  Yet there is a "I_IS_INVERTED" parameter defined on the Verilog library symbol for that primitive.

So can it support clock inversion or not??

 

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Moderator
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Registered: ‎08-08-2017

Re: BUFGCE_DIV inverted I input

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Hi @davemac22 

table 2-8 in the UG572 seems to be incorrect here. BUFGCE_DIV supports optional inversion on I pin .

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Moderator
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253 Views
Registered: ‎08-08-2017

Re: BUFGCE_DIV inverted I input

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Hi @davemac22 

table 2-8 in the UG572 seems to be incorrect here. BUFGCE_DIV supports optional inversion on I pin .

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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