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Observer george_mrch
Observer
748 Views
Registered: ‎01-29-2018

Bidirectional Source-Synchronous Interface between two FPGA

I'm trying to realize following type interface using SERDES primitives. FPGA B is a copy of FPGA A. But when I try to implement the scheme, I get from Vivado following critical warning and errors. As I understand is related with try place SERDESE primitives in the same IO bank, but clocking scheme does not allow it?How should I change my schema to get the specified implementation?



Thanks

critical.png
errors.png
Bidir_sourceSynchronous (1).jpg
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13 Replies
Moderator
Moderator
675 Views
Registered: ‎08-08-2017

Re: Bidirectional Source-Synchronous Interface between two FPGA

Hi @george_mrch 

The correct Bidirectional Signaling Using IDELAY/ODELAY with ISERSDES and OSERDES is as follows.

The clock and clock_Div inputs to the ISERDED and OSERDES  should be from common source.

Capture.JPG

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Bidirectional Source-Synchronous Interface between two FPGA

Are these of use as reference

https://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf

https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf

 

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Observer george_mrch
Observer
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Registered: ‎01-29-2018

Re: Bidirectional Source-Synchronous Interface between two FPGA

Thanks @pthakare . How in this case to implement Forward Clock form FPGA A to FPGA B? In UG is not specified. How do I in this case recieve Data with clock from FGPA B to FPGA A

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Moderator
Moderator
628 Views
Registered: ‎08-08-2017

Re: Bidirectional Source-Synchronous Interface between two FPGA

Hi @george_mrch 

Is the data rate different in transmitting from FPGA A to B and Vice a versa?

 

 

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Observer george_mrch
Observer
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Registered: ‎01-29-2018

Re: Bidirectional Source-Synchronous Interface between two FPGA

@pthakare 

Transmission data speed is the same.

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Observer george_mrch
Observer
598 Views
Registered: ‎01-29-2018

Re: Bidirectional Source-Synchronous Interface between two FPGA

@pthakare 

Here is what you need to get. I'm confused because I don’t understand how to implement a separate clock strobe for each direction

Untitled Diagram.jpg
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Scholar drjohnsmith
Scholar
590 Views
Registered: ‎07-09-2009

Re: Bidirectional Source-Synchronous Interface between two FPGA

Each FPGA needs to generate a clock to send with the data.

If an FPGA send data to two FPGAs it needs to send two clocks, one with each data , just as you have drawn,

In addition , each FPGA will need its own clock for its internal logic which runs constantly and from startup.

You then need to do clock crossing from the receive to the internal clocks
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Observer george_mrch
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Registered: ‎01-29-2018

Re: Bidirectional Source-Synchronous Interface between two FPGA

@drjohnsmith 

 

Maybe I did not understand you correctly. But it seems to me that SLK21 is not needed in this case? I can not understand: the 7 series allows you to use different sources of clock frequency for ISERDESE and OSERDESE. In this case, I can not do this.

SS.jpg
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Scholar drjohnsmith
Scholar
551 Views
Registered: ‎07-09-2009

Re: Bidirectional Source-Synchronous Interface between two FPGA

To use source syn clocking,

 

your Iseddes needs to be clocked by the received clock,

 

not certain thats possible  in the chip you have, give it a try.

     typical , high speed buses use i and o serdes, and these tend to be uni direcional , so they can have termination ,

              so your in a bit of a un usual place here.

 

 

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Observer george_mrch
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Registered: ‎01-29-2018

Re: Bidirectional Source-Synchronous Interface between two FPGA

@drjohnsmith 

Following from the UG and picture above, I can not use received clock for iserdes clocking. Does this mean that I basically can not implement the required scheme? As in this case, for example, implemented memory interfaces that allow bidirectional data and a clock?

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Scholar drjohnsmith
Scholar
523 Views
Registered: ‎07-09-2009

Re: Bidirectional Source-Synchronous Interface between two FPGA

What do you want to do ?

 

Interface between FPGAs as you have shown , or FPGA to DDR memory ?

If DDR memory, then use the memory wizard, there are special pins and functions to cover that you have to use,  special track constraints, tracks you have to feed out fomr the FPGA to the DDR and back  and the DDR chips have active / switched temrminatoin and PLL's on them.

If FPGA to FPGA, then, if you want to send stuff source syncronous, then you have to have clock with data, thats the definition of source syncronous.   Else use another method.

There are many other options out there to connect two FPGA's together, the current favorit is to use the GTx phys on th echips to run serial links at Gb/s ,

 

 

 

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Observer george_mrch
Observer
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Registered: ‎01-29-2018

Re: Bidirectional Source-Synchronous Interface between two FPGA

@drjohnsmith  

I need Interface between FPGAs.  But I do not understand how to send clock from FPGA 2 to FPGA 1. Because both ISERDESE and OSERDESE of FPGA1 and FPGA2 most operate with the same clock. This clock generate MMCM on the FPGA1 side, connect to ISERDESE and OSEREDSE in FPGA1 and this clock send to FPGA2 where this clock signal connect to ISERDESE and OSERDESE also. My question is what for send clock from FPGA2 to FPGA1? WHAT this signal will be clocked?Who will use it? After all ISERDESE and OSRDESE on the FPGA1 side use MMCM clock, they do not need transferred from FPGA2 clock?


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Observer george_mrch
Observer
508 Views
Registered: ‎01-29-2018

Re: Bidirectional Source-Synchronous Interface between two FPGA

@drjohnsmith 

Forgive me, but I feel stupid

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