05-23-2019 10:16 PM
I have a question regarding the boot process with Xilinx Zynq Ultrascale+ MPSoC device. Our custom board has XCZU2CG-2SFVA625I device and S25FL512SDPBHV310 Spansion Flash device.
We use multiboot method with one fsbl located at zero address and the other in the higher flash space.
Booting works fine most of the time. From time to time first golden fsbl (at zero address) fails to boot with CSU logging error 0x37 saying: "FSBL execution address is not in the OCM address range."
BootMode is set to QSPI32 and Spansion Flash device should be supported by Xilinx devices.
Do you have any advice about why booting fails eg.(1/10) with this error? Could it be that CSU read from flash fails?
Any help would be appreciated.
05-29-2019 09:53 AM
05-30-2019 12:39 AM
after some research, we found out that power on sequence was not by specifications. With modified POS this problem doesn't appear.
But then we encountered another problem. Randomly FSBL function FlashID Read returns wrong value with QSPI_REF_CLK set to 40Mhz and LPD_LSBUS_CLK set to 100 MHz. With additional research, we found out from #AR47579 that there is a restriction on different clock domain relations for ZYNQ-7000.
With increased QSPI_REF_CLK greater or equal then LPD_LSBUS_CLK problem disappears.
Is there any documentation regarding different clock domain relations on ZYNQ MP devices? I could not find any clock restrictions in UG1085 except ones that ZYNQ PS provides within GUI with maximum frequencies.