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652 Views
Registered: ‎06-21-2017

Clock Input

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I am trying to connect a differential (LVDS) clock to bank 66 of a XCZU9EG-ffvb1156.  I am using the IO Ports tab of the implemented design to assign pins.  Bank 66 is using a 1.8V VCCO.  DIFF_TERM is set to TRUE in the code.  I am trying to assign the _P side of the clock to Y4 which is labelled IO_L13P_T2L_N0_GC_QBC_66.  My understanding is that the GC indicates a clock capable pin and that the L13P means that it should be the P side of the LVDS.  The pull down does not show Y4, or any GC pins in bank 66.  I have not locked the input buffer or the MMCME4_ADV anywhere in my code. 

 

Does anybody have any thoughts as to why I can't assign the clock to this pin?

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Moderator
Moderator
599 Views
Registered: ‎02-09-2017

Re: Clock Input

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Hi @bruce_karaffa,

 

There are definitely a few different ways to assign physical pins to a port. I believe it should be done, ideally, before you run the implementation, since that information will be used by the P&R to optimize the network traces.

 

The way I do (and I think is the easiest way) is to add those as constraints to the xdc file, or yet to issue those commands via TCL.

 

So whenever I create a project, I first look into the document UltraScale and UltraScale+ FPGAs Packaging and Pinouts - UG575, and find which pins in my device are GC (and decide which ones I want to use).

 

Then I create an xdc file and add constraints like these:

 

create_clock -add -name sys_clk_pin -period 13.46 [get_ports SYSCLK_P]

set_property PACKAGE_PIN AK14 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_N]
set_property PACKAGE_PIN AK15 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_P]

Then, once I run the synthesis, those places are already applied and carry through the implementation as well.

 

Thanks,

Andre Guerrero

Product Applications Engineer

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2 Replies
625 Views
Registered: ‎06-21-2017

Re: Clock Input

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I locked down a number of other pins and re-implemented my design.  Sure enough the placer put the clock on Y4, just like I wanted all along.  Thanks Vivado 2017.2. 

 

I would mark this as solved, but a solution shouldn't leave me more confused than the original question.

0 Kudos
Moderator
Moderator
600 Views
Registered: ‎02-09-2017

Re: Clock Input

Jump to solution

Hi @bruce_karaffa,

 

There are definitely a few different ways to assign physical pins to a port. I believe it should be done, ideally, before you run the implementation, since that information will be used by the P&R to optimize the network traces.

 

The way I do (and I think is the easiest way) is to add those as constraints to the xdc file, or yet to issue those commands via TCL.

 

So whenever I create a project, I first look into the document UltraScale and UltraScale+ FPGAs Packaging and Pinouts - UG575, and find which pins in my device are GC (and decide which ones I want to use).

 

Then I create an xdc file and add constraints like these:

 

create_clock -add -name sys_clk_pin -period 13.46 [get_ports SYSCLK_P]

set_property PACKAGE_PIN AK14 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_N]
set_property PACKAGE_PIN AK15 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_P]

Then, once I run the synthesis, those places are already applied and carry through the implementation as well.

 

Thanks,

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post