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Contributor
Contributor
364 Views
Registered: ‎10-29-2018

Clock Wizard frequency limitiations

I'm using the VCU108 develeopment kit. I'd like to be able to synthesize a 1.2GHz clock. It looks like the clock wizard has a limitations of 933 MHz. Even at 800 MHz, I'm getting a warning saying that the output frequency is out of range for the buffers. Any ideas? 

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3 Replies
Scholar watari
Scholar
346 Views
Registered: ‎06-16-2013

Re: Clock Wizard frequency limitiations

Hi @threedtramp 

 

Would you refer page 38 of this data sheet ?

 

https://www.xilinx.com/support/documentation/data_sheets/ds893-virtex-ultrascale-data-sheet.pdf

 

Unfortunetely, you can not achive a 1.2GHz clock in this PLL.

 

BTW, what purpose do you use PLL ? for DRAM ? for serial IO ? or other ?

 

It might be able to achive 1.2GHz clock, if the purpose is for DRAM or serial IO...

 

Best regards,

 

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Contributor
Contributor
329 Views
Registered: ‎10-29-2018

Re: Clock Wizard frequency limitiations

It's for serial IO as well as internal FPGA operations. But not sure why the clocking wizard would know or care what the application is. Is there another method to accomplish this?

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293 Views
Registered: ‎01-22-2015

Re: Clock Wizard frequency limitiations

@threedtramp 

As watari says, UG893 is your guide to capabilities of the Virtex Ultrascale, XCVU095, found in the VCU108 kit. Unfortunately, very few components in this FPGA (or any FPGA) can operate at your clock speed of 1.2GHz. However, if you only need this clock speed for a serial port then you’re in luck!  Note that Table 37 of UG893 shows the PLL has a clock-output called CLKOUTPHY with a maximum frequency 2670MHz!  This output is specifically designated for driving an amazing group of circuits to which Xilinx has given the boring name of “physical-layer” (PHY) or RXTX_BITSLICE (see UG571, Chap 2, Native Primitives).

Xilinx provides IP called the High Speed SelectIO Wizard (see PG188) that helps us work with the PHY.  PG188 says the PHY can achieve serial interface speeds of up to 1600 Mb/s.  Further, the PHY supports a serialization/deserialization factor of up to 8. This means that the FPGA fabric can talk to the PHY over an 8-bit wide parallel interface. So, if the PHY serial port is running at 1200 Mb/s (as you want) then the FPGA fabric needs to be clocked at only 1200/8=150MHz to keep up with the data rate.

Cheers,
Mark

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