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Adventurer
Adventurer
207 Views
Registered: ‎11-18-2017

Clock tree distribution inside a FPGA.

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Hello.

 

I'm using Vivado 2018.2 and a KCU116 board which is equipped with Kintex UltraScale+ FPGA (xcku5p-ffvb676-2-e).

After Implementation, I can see the overall floorplanning in the device tab.

 

In the FPGA, I found a region which has no slices as below figure 1.

 

fp1.png

figure 1.

 

when I enlarge the screen, actually the region has some logics as below figure 2.

 

fp2.png

figure 2.

 

As I enlarge once more, I can see some buffers (BUFCEs) in that region as below figure 3.

 

fp3.png

figure 3.

 

when I clicked the Routing Resources as below figure 4,

 

fp4.jpg

figure 4.

 

I can see lots of connections as below figure 5.

 

fp6.png

figure 5.

 

My question is, what is this regions?

This regions are between (SliceX?Y29 and SliceX?Y30),  (SliceX?Y89 and SliceX?Y90),  (SliceX?Y149 and SliceX?Y150) and  (SliceX?Y209 and SliceX?Y210). 

I think they might be related with the clock tree (maybe they are the clock path).

 

Thank you for your help. 

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Teacher
Teacher
191 Views
Registered: ‎07-09-2009

Re: Clock tree distribution inside a FPGA.

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Probably you are correct.

As an aside,the graphics viewer is only loosely related to the real chip, its a graphical representation of the real chip, which is a more 3D structure,

Id understand its also deliberately obtuse so as not to give away industrial secrets.


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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1 Reply
Highlighted
Teacher
Teacher
192 Views
Registered: ‎07-09-2009

Re: Clock tree distribution inside a FPGA.

Jump to solution
Probably you are correct.

As an aside,the graphics viewer is only loosely related to the real chip, its a graphical representation of the real chip, which is a more 3D structure,

Id understand its also deliberately obtuse so as not to give away industrial secrets.


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post