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dpaul24

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09-27-2018 12:54 AM - edited 09-27-2018 12:57 AM

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Registered:
08-07-2014

Hi,

We all know that the synth report contains a table that contains the number of resources utilized. I am particularly interested in the number of LUTs utilization counts (lets us ignore the BUF*, MMCM/PLL, DSP-slices, BRAMs, etc). Now there are stuff like LUT1, LUT2, LUT3, LUT4, LUT5 and LUT6. The synth report will contain the amount utilized by each of these LUTs.

Now lets assume that someone asks me if I can find out how many LUTs will be utilized if I want to implement a 100,000 gate ASIC in a Ultrascale device. How do I find that? **How can I *roughly* map the gate equivalent count to the LUTs count? **Any suggestions?

I have referred to this 2015 blog from Synopsys and there is a reference to Xilinx in it:

https://blogs.synopsys.com/breakingthethreelaws/2015/02/how-many-asic-gates-does-it-take-to-fill-an-fpga/

It says, *1* LUT = 6 Two input NAND Gate equivalent (go try it!)*

What I don't understand is what is meant by "LUT". Because in Xilinx devices we have LUT1, LUT2, LUT3, LUT4, LUT5 and LUT6. Is it indicating that I combine all the LUT* counts from my synth report and use that value in comparing with the gate equivalent count?

Any answers? Vague answers? Suggestions?

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1 Solution

Accepted Solutions

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avrumw

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01-02-2019 08:39 AM

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Registered:
01-23-2009

Be aware - the cell in the FPGA is a 6-input 2-output LUT. This LUT can be used in a whole variety of ways for implementing anywhere from a one input one output function (which would use the LUT1 personality of the LUT6), to a 6 input one output function (which would use the LUT6 personality) to a variety of combinations of functions that use no more than 6 inputs and provide no more than 2 outputs (which would use any of LUTx_x personalities). But these are all still using a single LUT.

Yes, if your design uses WAY more LUT2s than LUT6s then you will get one gate count, whereas if you use way more LUT6s than LUT2 then you will get a much larger equivalent ASIC gate count. The reality is that the synthesis tool will try and use LUTs "appropriately" - you will probably see fewer LUT2s than LUT6s.

So, as you can see, even from this analysis alone, you can get widely different answers. A single LUT behaving as a LUT2 can be the equivalent of one NAND2 gate, or can be the equivalent of a 6 input complex gate, which would represent 7.5 gates (take a 6 input AND gate constructed of 5 AND gates, each representing 1.5 gates due to the inversions). There are also free inverters on the inputs, the MUXF7, MUXF8, MUXF9 cells and the CARRY4 chain which all implement combinatorial logic **outside** the LUT6. If these are used, you can get LOTs of gates in one CLB...

And don't forget the flip-flops - in some designs they dominate the "area" calculations - these are separate from the LUTs in the FPGA, whereas they may be lumped together in "gate count" in an ASIC"...

Even the question "What is an ASIC gate" is a complex one to answer - are you asking "What is the area in units of min-sized NAND2 instances" or "What is the combinatorial instance count" - which are two VERY different questions.

And the answer will change **drastically** based on the design - a design that runs at 10MHz will have very different characteristics than one that runs at 500MHz - in ASIC, you may end up with much smaller sized gates for the 10MHz design, but much larger (higher drive) gates for the 500MHz design - but these will likely use the same number (or similar number) of LUTs in the FPGA.

So the answer is "it all really depends". So the "guesstimate" of 3-8+ "gates" per "LUT" could all be in the right ballpark.

Avrum

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xilinxacct

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12-22-2018 09:36 AM

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10-23-2018

I 'think' this is what you are asking... The LUT in an Ultrascale is a 6_2 (six inputs, and 2 outputs)... Other FPGA families I think were mostly 4_2...

Hope that helps

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dpaul24

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01-02-2019 06:36 AM - edited 01-02-2019 06:39 AM

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Registered:
08-07-2014

Thanks for trying to answer.

What you have mentioned is an information and I will register it. :-)

But I still don't understand the difference here : *Because in Xilinx devices we have LUT1, LUT2, LUT3, LUT4, LUT5 and LUT6.*

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lowearthorbit

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01-02-2019 07:17 AM

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Registered:
09-17-2018

LUT1, 2, etc. tells you:

How much of the LUT was used. So, for example, if logic had 6 inputs, and one output, it will always fit it a LUT6 (given it is not optimized to use less than all 6 inputs). As mentioned by Synopsis, if 6 2 input NAND gates in some arrangement of 6 inputs, one output are used, that fits in a LUT6. So, a reasonable estimate would look at how many LUT (disregard 1, 2, 3 ...), multiply by 6, and that is the rough first guess at ASIC gates. Looking at DFF count, that is your flop count.

l.e.o.

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xilinxacct

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01-02-2019 08:09 AM

3,631 Views

Registered:
10-23-2018

LUT1 Macro: 1-Bit Look-Up Table with General Output

LUT1_D Macro: 1-Bit Look-Up Table with Dual Output

LUT1_L Macro: 1-Bit Look-Up Table with Local Output

LUT2 Macro: 2-Bit Look-Up Table with General Output

LUT2_D Macro: 2-Bit Look-Up Table with Dual Output

LUT2_L Macro: 2-Bit Look-Up Table with Local Output

LUT3 Macro: 3-Bit Look-Up Table with General Output

LUT3_D Macro: 3-Bit Look-Up Table with Dual Output

LUT3_L Macro: 3-Bit Look-Up Table with Local Output

LUT4 Macro: 4-Bit Look-Up-Table with General Output

LUT4_D Macro: 4-Bit Look-Up Table with Dual Output

LUT4_L Macro: 4-Bit Look-Up Table with Local Output

LUT5 Primitive: 5-Input Lookup Table with General Output

LUT5_D Primitive: 5-Input Lookup Table with General and Local

Outputs

LUT5_L Primitive: 5-Input Lookup Table with Local Output

LUT6 Primitive: 6-Input Lookup Table with General Output

LUT6_2 Primitive: Six-input, 2-output, Look-Up Table

LUT6_D Primitive: 6-Input Lookup Table with General and Local

Outputs

LUT6_L Primitive: 6-Input Lookup Table with Local Output

If that is what you are looking for, please mark as solution accepted. (and Kudos welcomed :-)

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avrumw

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01-02-2019 08:39 AM

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Registered:
01-23-2009

Be aware - the cell in the FPGA is a 6-input 2-output LUT. This LUT can be used in a whole variety of ways for implementing anywhere from a one input one output function (which would use the LUT1 personality of the LUT6), to a 6 input one output function (which would use the LUT6 personality) to a variety of combinations of functions that use no more than 6 inputs and provide no more than 2 outputs (which would use any of LUTx_x personalities). But these are all still using a single LUT.

Yes, if your design uses WAY more LUT2s than LUT6s then you will get one gate count, whereas if you use way more LUT6s than LUT2 then you will get a much larger equivalent ASIC gate count. The reality is that the synthesis tool will try and use LUTs "appropriately" - you will probably see fewer LUT2s than LUT6s.

So, as you can see, even from this analysis alone, you can get widely different answers. A single LUT behaving as a LUT2 can be the equivalent of one NAND2 gate, or can be the equivalent of a 6 input complex gate, which would represent 7.5 gates (take a 6 input AND gate constructed of 5 AND gates, each representing 1.5 gates due to the inversions). There are also free inverters on the inputs, the MUXF7, MUXF8, MUXF9 cells and the CARRY4 chain which all implement combinatorial logic **outside** the LUT6. If these are used, you can get LOTs of gates in one CLB...

And don't forget the flip-flops - in some designs they dominate the "area" calculations - these are separate from the LUTs in the FPGA, whereas they may be lumped together in "gate count" in an ASIC"...

Even the question "What is an ASIC gate" is a complex one to answer - are you asking "What is the area in units of min-sized NAND2 instances" or "What is the combinatorial instance count" - which are two VERY different questions.

And the answer will change **drastically** based on the design - a design that runs at 10MHz will have very different characteristics than one that runs at 500MHz - in ASIC, you may end up with much smaller sized gates for the 10MHz design, but much larger (higher drive) gates for the 500MHz design - but these will likely use the same number (or similar number) of LUTs in the FPGA.

So the answer is "it all really depends". So the "guesstimate" of 3-8+ "gates" per "LUT" could all be in the right ballpark.

Avrum

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dpaul24

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01-03-2019 12:45 AM

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Registered:
08-07-2014

Thanks @xilinxacct for that list.

I think @avrumw has best answered my question.

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FPGA enthusiast!

All PMs will be ignored

--------------------------------------------------------------------------------------------------------

FPGA enthusiast!

All PMs will be ignored

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