Data Capture LVDS output using High Speed Select I/O

[achen58]

I want to create an LVDS interface between the ADC and FPGA. I saw that there are tools in Vivado to build interfaces like High Speed Select I/O wizard. My question is, is this the easiest way to create the interface or is there any better options out there? I am relatively new to using Vivado and VHDL so any direction would be helpful!

[sandrao · Accepted solution]

Hi @achen58 

Which ADC are you interfacing too? The data rate and number of channels would impact which I would recommend.

The HSSIO Wizard is a good approach if you are able to fit the interface into one bank. The Built In Self Calibrate means the data to clock alignment is handled if the board means the Timing Budget : https://www.xilinx.com/support/answers/68618.html

It is problematic if its a very wide interface that the ADC probably only send one bit clock and the HSSIO needs a capture clock per bank.

Otherwise you'd need to use Component Mode and instantiate the IDELAY & ISERDES via VHDL and unfortunately we do not have a ADC Xapp for UltraScale.

The best UltraScale Component Mode Xapp is the 7:1 Video Xapp, its not an exact match to your application but should be a good starting point. 

http://www.xilinx.com/support/documentation/application_notes/xapp1315-lvds-source-synch-serdes-clock-multiplication.pdf

[achen58]

Hi @sandrao

I am interfacing with an ADC similar to the AD9642. My sampling rate is 300Mhz and is running on 7 LVDS data line and 1 LVDS clock.

[sandrao]

Hi @achen58 

300Mhz of a sampling rate is actually below the HSSIO Wizard limit. So you will need to use Component Mode, Xapp1315 is the best starting point that I can suggest, but you will need to change it suit the AD9642.

Sandy

[achen58]

Hi @sandrao 

I just verified with the HSSIO user guide and it says the required sampling rate is between 300Mb/s ~ 1,600Mb/s. Can HSSIO still be used for this case then or is it on the low end of the spectrum?