06-06-2019 11:52 AM
I am using a XCKU115 FPGA in which I have a pair of serdes output pin TXP and TXN, have to transmit data 0xf83e0 which is in binary - 1111 1000 0011 1110 0000 which is 5 1s followed by 5 0s, and it will make a clock pattern on my output.
I have it set in such a way that the expected clock output should be of 148.5 MHz. I verified this from simulations to be correct.
But when I use this in my FPGA, I observe a jitter in the clock going out. The clock varies from 148.5M to 157.3M which is above 5% deviation and is a one bit error in 20 bit user widths.
I observe the txuserclk_out from the transceivers and they have very less jitter (in KHz), but the data pin output varies in MHz?
The feedback clock for the GTH is done by including the User clocking core inside the GTH IP itself. Should I provide the feedback clock which comes from the logic instead? The former method is how it was implemented previously in our GTX FPGAs.
Any help here is much appreciated!
06-06-2019 11:59 AM
How are you measuring the output frequency? How do you know what the variation is? The jitter? From what you describe it should 'just work.'
Does your design meet timing?
06-06-2019 12:29 PM
I have differential probes on the output pins and I have a histogram analyzer on the frequency it measures. I am thinking it is jitter but I have not exactly captured the moment where the frequency change happens. I will keep looking.
Device may not have completely met timing. But I am running at a far lower rate than what I attempt to close timing.
The problem is, this data line is a HDMI output and when fed to a protocol analyzer it reports the frequency of 148.5M and 157.3M on the clock lane as well. That is what got me scoping.
06-06-2019 12:44 PM
Also do you know of any way that I could get access to GTH TX pins internally? I would like to extract this clock going out internally and put it to a debug bus for more analysis.
06-06-2019 02:22 PM
Why are you using a Gigabit Trasceiver to generate a clock? The FPGA has perfectly good PLLs/MMCMs for that...
What is the REFCLK of your GT?
06-06-2019 02:39 PM
Like I said earlier, I am trying to validate a design which has 4 lane TX. One of the protocols which can be used on this is HDMI, so one of the lanes becomes clk in HDMI.
Ref_clk of serdes is 37.125M here and it would generate a 148.5M clk in the 4th lane(with my pattern) which should work as per my simulations. And it does give 148.5M here but it is not consistent.