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Visitor lsisaxon
Visitor
1,167 Views
Registered: ‎03-06-2018

Decoupling capacitors for XC-ZU3EG

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Hi,

 

Can anyone advise if there is a need for 1x 100uF and 1x 4.7uF for VCC_PSBATT rail which draws less than 5uA? Will a 10uF or even a 1uF suffice? I am powering it using an ultra low quiescent 1.35v LDO (TPS709135) from a single cell LiPo battery.

 

Also, it was mentioned in the UG583 document also that the large 680uF bulk capacitors for the VCCINT is to cater for ripples down to 100kHz. If my switching regulators are running >1MHz, is it still necessary for the 680uF or can I reduce the size to save some board space? At the moment, I am designing in 4x 220uF X5R in place of the 1x 680uF. Will there be a concern?

 

Thanks!

 

Best regards,

Saxon

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Xilinx Employee
Xilinx Employee
1,521 Views
Registered: ‎06-30-2010

Re: Decoupling capacitors for XC-ZU3EG

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in ug 583 we document the assumptions made when generating the decoupling capacitors. Its page 17: http://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

The tables have to cater for a large number of applications so it is hard to get an exact table but we try and cover the majority of designs. For designs that have a larger requirement, they need to do a PDN simulation. If you have a much less requirement a PDN simulation could be done as well if you did want to reduce the number of caps. But in general, I would recommend sticking to the tables listed unless you either do a thorough analysis or you just like to live dangerously!
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Scholar drjohnsmith
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1,129 Views
Registered: ‎07-09-2009

Re: Decoupling capacitors for XC-ZU3EG

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Easy answer is yes to both questions.

 

BUT,

 

your into the world of needing to simulate the power supply.

 

The guides are just that, 

   one can get away with much less,  

        I tend to use high frequency DCDC and ceramics, and yes you can significantly lower the requirements,

             but every now and then you will be caught out by 'random' problems,

                  and then your into a world of hurt, 

 

which is when you wish you had stuck to the guides, and / or simulated.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Visitor lsisaxon
Visitor
1,117 Views
Registered: ‎03-06-2018

Re: Decoupling capacitors for XC-ZU3EG

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Thanks! I like your reply. So I guess to simplify things, I should just stick with the recommended decoupling solutions.

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Scholar drjohnsmith
Scholar
1,113 Views
Registered: ‎07-09-2009

Re: Decoupling capacitors for XC-ZU3EG

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If in doubt, don't 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
1,522 Views
Registered: ‎06-30-2010

Re: Decoupling capacitors for XC-ZU3EG

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in ug 583 we document the assumptions made when generating the decoupling capacitors. Its page 17: http://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

The tables have to cater for a large number of applications so it is hard to get an exact table but we try and cover the majority of designs. For designs that have a larger requirement, they need to do a PDN simulation. If you have a much less requirement a PDN simulation could be done as well if you did want to reduce the number of caps. But in general, I would recommend sticking to the tables listed unless you either do a thorough analysis or you just like to live dangerously!
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos