Delaying clock in UltraScale+

[navoda.perera.abb]

I am trying to implement an lvds receiver on an UltraScale+ device (Ultra96 board) referring the xapp524.

However, i also read that IDELAYE3 elements of UltraScale architecture should be not be used to drive clocks, which is done with IDELAYE2 in xapp524.

So what is the recommended method to do this? Can i use an MMCM to dynamically delay the clock and achieve the same result?

[pthakare · Accepted solution]

Hi @navoda.perera.abb 

Yes, MMCM should be used here.

Form UG.

Clocks should not be delayed using an IDELAYE3, because the IDELAY cannot directly route to the global clock buffers. When clocks must be delayed,
use an MMCM or PLL for clock generation, and delay the clocks using the fine-phase shift capabilities.

Fine phase shift is documented in clocking user guide

https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf

[navoda.perera.abb]

On a different note, the device i am using is a Zynq UltraScale+ MPSoC ZU3EG (AvNet Ultra96 board).

As i understood from the documentation, the high speed LVDS clock input should be given to HP_GPIO_CC+/- pins at J5 (IO_L16N_T2U_N7_QBC_AD3N_65) and H5 (IO_L16P_T2U_N6_QBC_AD3P_65).

However, this results in a DRC PLCK-58 (Sub-optimal placement for global clock-capable IO pin and BUFG pair) error, which suggested to add an extra BUFG between the MMCM and the BUFIDS. Even after this, i had to add "CLOCK_DEDICATED_ROUTE FALSE" to demote it to a warning and get the placement done.

My 2 main questions are:

1. Even with the warning, if the design doesn't fail timing am i good to go?
2. Can i use one of the other differential input pairs in bank 65 to maybe take in the clock and avoid this warning? (I am not sure how exactly to determine whether they are clock-capable)