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904 Views
Registered: ‎01-22-2015

FPGA board planning

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-am preparing for some bored/board work, hoping to upgrade FPGA on existing board to Kintex-UltraScale+ (KU5P – thanks u4223374).

 

My “must read” list includes the following:

  • ug949  UltraFast Design Methodology               
  • ug583  UltraScale Architecture PCB Design
  • xtp427 Ultrascale-plus-schematic-review-checklist
  • Advice for Board Designers - on Forum <here>             
  • Vivado use of I/O Planning Project

-any other reading-recommendations, reminders, cautions, encouragement?

 

Also, xmp102 <UltraScale Product Selection Guide> ,  has table on page 7 saying there is “footprint capability” between UltraScale KU035-A676 and UltraScale+ KU5P-A676.   If I design board for one of these devices, can I really use either device – really?

 

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Moderator
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1,120 Views
Registered: ‎07-23-2015

Re: FPGA board planning

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markg@prosensing.com You pretty much covered the docs needed for migration and design of your board. They are a good stating point to get you off the blocks. Once you finish going through them and have queries, feel free to post them here. 

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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2 Replies
823 Views
Registered: ‎01-22-2015

Re: FPGA board planning

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I suspect that the answers are:

 

     -any other reading-recommendations, reminders, cautions

Careful reading of ug949 should refer you to all the other necessary reading.

 

     If I design board for one of these devices, can I really use either device – really?

Yes – sorta.   I find much good reading about this in chapter-4 of ug583 and starting on page-31 of ug575.  Footprint compatibility means that nothing catastrophic will happen (eg. a power pin on one device is a ground pin on another device).   However, here are just a few of the “migration considerations” found in ug583.

 

  • pg153: If migrating from a bigger device to a smaller device within the same package, there exists the potential for some I/O and transceiver banks to not be bonded out or present on the smaller device.
  • pg154: Package dimensions for UltraScale devices can vary from one package to another, so care must be taken in system design to ensure that changes in length, width, or height do not interfere with other components in the system(board).
  • pg157: .. certain multi-bank interfaces (such as memory or transceiver) could be impacted because … bank location on the die may change even though pin-outs do not
  • pg158: In a small number of cases, an HR bank in one device might become an HP bank … it is advisable to use only 1.8V I/O standards so that any move from HR to HP banks is not affected
  • pg159: migration could result in swapping between GTH and GTY transceivers
Moderator
Moderator
1,121 Views
Registered: ‎07-23-2015

Re: FPGA board planning

Jump to solution

markg@prosensing.com You pretty much covered the docs needed for migration and design of your board. They are a good stating point to get you off the blocks. Once you finish going through them and have queries, feel free to post them here. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post