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Explorer
Explorer
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Registered: ‎12-07-2018

Global Clock Output pins on Zynq Ultrascale+ FPGA

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Hello, I am using the XCZU7EV-2FFVF1517I Zync Ultrascale+ FPGA. I am reading the Zynq UltraScale+ Device Packaging and Pinouts document to search for which pins are considered Global Clock pins. I see on page 23 is states that GC are pins connected to the Global Clock buffers and the pin is an input. I'm looking for which pins are outputs of the Global Clock buffers, or I would like to say are dedicated output pins for clocks.

Can anyon help me please?

 

Thank you,

Joe

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Explorer
Explorer
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Registered: ‎03-31-2016

Re: Global Clock Output pins on Zynq Ultrascale+ FPGA

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There are no dedicated clock outputs.  If you use an ODDR with the inputs tied 0 and 1 you will get the clock of the ODDR as an output.   You can then use the normal data pin methods to  control the skew.  

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Explorer
Explorer
267 Views
Registered: ‎03-31-2016

Re: Global Clock Output pins on Zynq Ultrascale+ FPGA

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There are no dedicated clock outputs.  If you use an ODDR with the inputs tied 0 and 1 you will get the clock of the ODDR as an output.   You can then use the normal data pin methods to  control the skew.  

Explorer
Explorer
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Registered: ‎12-07-2018

Re: Global Clock Output pins on Zynq Ultrascale+ FPGA

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Hello, thank you for responding to my message. I've seen dedicated outputs on other smaller less dense FPGA so this is a surprise not to see these outputs in the Ultrascale+ devices. Oh well, life goes on. Thank you for responding to my message. Joe
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Explorer
Explorer
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Registered: ‎12-07-2018

Re: Global Clock Output pins on Zynq Ultrascale+ FPGA

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