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Explorer
1,722 Views
Registered: ‎07-10-2013

## HARD_SYNC Primitives and Block RAM Columns

UG574 (v1.5) indicates on p.52 that "Four [HARD_SYNC] synchronizers are located in the horizontal clock spine in the middle of each of the block RAM columns...".

How can the number of block RAM columns (and thus, the number of HARD_SYNC primitives) be determined for a given device?

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6 Replies
Highlighted
Scholar
1,713 Views
Registered: ‎02-27-2008

By reading the referred to reference,

UG572.

(not saying it is the best way to represent the information, but it is how it was done...   --you need the info in 571 AND 572 to figure it out)

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
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Registered: ‎07-10-2013

Austin,

Thanks, however it is not particularly obvious (at all) what information in UG571 and UG572 would be used to determine this.

So, taking the opposite course, specifically for a KU11P device, how many block RAM columns are present?

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Scholar
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Registered: ‎02-27-2008

OK,

That was fun (NOT).  From ds890, we get 600 BRAM, from ug572, we get there are 12 BRAM high CR (that the horizontal spline is in the middle of (from ug574)).  So, 600/12 = 50 CR.  With 4 hard_sync per CR (again from ug574), that makes 50x4=200.

I welcome corrections to my math and interpretation!

It is possible that the width is 2 BRAM in a CR, so that would cut the number in half, to 100.  I am not too clear on that (also from a figure in 574).  Cannot say that was an easy question to answer (as I did not answer it for certain).  I tend to think it is all easy to figure out, until I cannot do it myself, which then teaches me that some things are definitely not well documented as I had hoped.

So? Anyone out there know the answer?  Where is it documented?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
1,657 Views
Registered: ‎07-10-2013

Austin,

Thanks for walking through the numbers.  While waiting for anyone to confirm your information, I'd appreciate it if you would add yur expertise to another, semi-related post:

https://forums.xilinx.com/t5/UltraScale-Architecture/Built-in-Asynchronous-FIFO-Error-Rate/m-p/828318#M5961

Highlighted
Scholar
1,644 Views
Registered: ‎02-27-2008

Nothing to say,

Metastability in hardened features is designed to be in the worst case, far smaller than the hard FIT rate.  Thus, the probability the device fails is far more likely than the hard synchronizer fails.  Common in hardened IP blocks like FIFO/BRAM.

The most important lesson I learned from Western Electric Quality engineers many years ago is you do not need to be concerned about failure for anything less that the hard failure rate.  It will make no difference in the field if you improve that which does not matter:  wasted time and money.  Western Electric 'works' in Massachusetts was one of the largest factories in the world at the time, manufacturing almost everything for AT&T and the Bell system.

There are exceptions to this.  If you MUST, you need to contact your local sales office, sign a NDA, to get what is basically the same answer I have detailed above.  On Xilinx letterhead.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
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Registered: ‎07-10-2013

Austin,