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Visitor
Visitor
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Registered: ‎06-12-2019

High Speed IO Module

  • High Speed IO module has the beta version in case of Bi-Direction IO. Can we get the proper version?

  • High Speed IO module has maximum interface speed is 1600, if we want to increase then what is the maximum speed and how we can achieve it? is there any setting in RXTX_BITSLICE_CONTROL?

  • If we want to reset internal read fifo in RXTX_BITSLICE without affecting other logic then how we can reset it? 

  • Any additional informations on how RXTX_BITSLICE utilized at high-speed interface.
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Xilinx Employee
Xilinx Employee
352 Views
Registered: ‎05-07-2019

Hi,

  1. Xilinx recommendation is to use component mode for Bidirectional IO. For your reference, please have a look at the answer record link below      https://www.xilinx.com/support/answers/69471.html
  2. The maximum data speed supported by High speed IO is 1600 Mb/s where as in component mode the maximum is 1250Mb/s. You can’t increase more than that.
  3. It’s not possible to reset the FIFO in RXTX_BITSLICE because it’s a part of BITSLICE.
  4. The UG571 and XAPP1274 is a very good resource for the information about RXTX_BITSLICE.

         UG571- https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf  (page-202)

        XAPP1274- https://www.xilinx.com/support/documentation/application_notes/xapp1274-native-high-speed-io-interfaces.pdf

 

Kind Regards,

Kasthuri.