12-09-2014 12:42 AM
As we were trying to use DSP48E2 we could not find documentation on how to configure this in Vivado, which hardware platform to select zynq..etc also how to perform XOR operation using DSP48E2.Kindly can anyone help us or provide documentation or pointers on how to go about this.
12-14-2014 09:53 PM
12-09-2014 01:00 AM - edited 12-09-2014 01:02 AM
For Details on HDL coding styles and attribute information refer to UG901.
The UG479, has the design considerations and specifics of DSP48 in 7-series which includes zynq.
For Ultrascale devices refer to this link
12-14-2014 08:35 PM
Thanks for the reply.In ultrascale 579 he tells about setting of ALUMODE and OPMODE .we are trying to do it in C not in HDL is this possible if so any snippet code on how to do that??
12-14-2014 09:53 PM
12-16-2014 10:41 PM
Thanks for your reply.that means that I cannot configure ALUMODE and OPMODE using any C directive?? and also need to convert C code to HDL code using HLS to access the same...then if I write a XOR operation in C using HLS this will use normal LUT's which means I cannot force HLS to use DSP48E2 using C right??
12-16-2014 10:46 PM
also do you have any code snippet where we can do an XOR in DSP48E2 which has both C as well as HDL code using HLS so that we get an idea and run the same on the HLS tool???
12-16-2014 11:54 PM - edited 12-16-2014 11:57 PM
To be frank I am not sure even HDL synthesizers from Xilinx infer XOR operations in DSP48E. I haven't had a case where I needed such a wide XOR block. I think it's pretty much hopeless to get HLS to infer such a specific feature. You should ask in HLS forum; maybe someone from Xilinx can give some suggestions.
PS it seems someone else is interested in the same question: http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/How-to-force-HLS-to-implement-XOR-operation-using-DSP48/td-p/552431
12-17-2014 01:06 AM
when you refering as AXI path this means that it will have to support AXI interface protocol and also what do you mean by MB design (master board) so as to interface this and then use the DSP48E2 ??
12-17-2014 01:14 AM
Also say if I am using signal processing chain which would include all logical operations and also MAC and add sub ..etc then to do all these if we need DSP48E2 ..does that mean for all these you would require AXI slave interface and MB design so that all the processing blocks would work in maximum optimized mode????
12-17-2014 08:00 AM - edited 12-17-2014 02:35 PM
I mentioned microblaze as an example because you need some processor to run the rest of the C code. But that was an assumption on my part that you would want to partition your design into C and hardware. I am not sure what exactly you are trying to do.
About using all the features of DSP48E, you should know that XOR feature is exclusive of multiplier and accumulator in DSP48E so at one time you can use one or the other. Again I am pretty sure (and one Xilinx employee confers) inferring XOR in DSP48E can't be done by HLS.