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artisticzhao
Observer
Observer
972 Views
Registered: ‎10-29-2019

How to use RF data converter which controlled by PS to generate some waves

Hello, I'm working on build a QPSK transmitter by ZCU111 board.

Now, I'm a layman to use the RF data converter IP core.

I refer the SDK's rfdc_v5_0/xrfdc_read_write_example.c And I find that this example only show how to configure the IP. 

I think I need a tutorial to teach me that use AXI-Stream to send data to RFdc. 

Thanks : )

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4 Replies
pthakare
Moderator
Moderator
957 Views
Registered: ‎08-08-2017

Hi @artisticzhao 

To start with please refer the product guide for Data coneverter IP

https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_2/pg269-rf-data-converter.pdf

The next step is to check the example design section in the product guide. After configure the IP as per your requirement , Generate the example design and see how AXI4 stream interface works.

The complete example design can be opened as a separate project by right-clicking the core in the project hierarchy after it has been customized using the IP catalog. Right-click the .xci file in the Design Sources hierarchy in the Sources window and select Open IP Example Design. This opens a new Vivado® IP integrator project in a new window with a complete RF Data Converter IP example design.

 

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artisticzhao
Observer
Observer
939 Views
Registered: ‎10-29-2019

Thank you for your reply.

I have read the pg269 and checkout the Vivado IP example design. The example design don't connect with the PSfig 1fig 1

When I try connect the s_axi with the PS(fig 2), there are some errors(fig 3).

fig 2 connect to PSfig 2 connect to PS

fig 3 errorsfig 3 errors

Regards

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zhendon
Community Manager
Community Manager
812 Views
Registered: ‎08-30-2011

Hello,

Yes, as you can see that, example design doesn't include the processor. DAC source module is used for feeding the data to DAC.

You can add the processor yourself and please be noted that dac1_axi_clk is DAC's fabric clock and it shoul d be driven by the same clock source from DAC reference clock. So I recommend you use the clock output from RFSoC IP "clk_dac1" to drive this clock.

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Registered: ‎01-06-2020

Hi @artisticzhao, I'm in the same boat as you, I added the Zynq, but in my case, I enabled all DAC and all ADC, and now I'm trying to drive with my own RTL, however, I control and feed/fetch these units using the ARM  and the PL-DDR4, and this is where quite a few problems showed up, like I tried to use an ILA and that is when I discovered that there was no clock coming out of the DAC, for example, because once I tried to read the ILA, on he manager screen on vivado it complained of no clock being driven and I connected it to the clock from the dac0_clk, passing into a clk_wizard to pump it to 500 MHz, but it didn't seem to have worked.

Let me know if you had any success on this since I'm working on getting my own design to work in this platform instead of the example design since it seems is the only design anyone knows how to make work on the RF devices

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