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aaron_holliday
Adventurer
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Registered: ‎01-26-2017

I/O range for LVDS pins on FMC

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Hi, this is a couple of interface / Select IO related question for ultrascale architectures.

 

In the user guide for the KCU105, p71 has this table:

fmc_io_question.PNG

In this table the I/O standard is not written for M2C and C2M FMC pins. Is it assumed to be LVDS for these signals? 

Another question: The documentation states that the FMC connectors can support x differential signals or 2x single ended signals. Does this just mean that we use any signal_P and signal_N differential signals as independent single ended signals? If this is the case, what I/O standard do these pins adhere to then? (LVCMOS18, or LVCMOS33) or something else? 

 

Apologies if this is in the Ultrascale SelectIO document, I did check it but might have missed it.

 

Regards,

Aaron

--- Estimated Development time: 2*Pi*(planned completion date) ---
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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

The  M2C and C2M FMC pins are GT pins Table 1-11 details the GT connections.

 

When you are picking an IOSTANDARD if you are using the differential pairs would be limited to standards supported for the Vcco of the bank, you can use an internal Vref. As the bank is powered at 1.8V it would need to an IOSTANDARD supported for Vcco = 1.8V

 

Tablw 1-77 give the Vcco requirements for each IOSTANDARD. 

Thanks,

Sandy


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sandrao
Community Manager
Community Manager
5,254 Views
Registered: ‎08-08-2007

The  M2C and C2M FMC pins are GT pins Table 1-11 details the GT connections.

 

When you are picking an IOSTANDARD if you are using the differential pairs would be limited to standards supported for the Vcco of the bank, you can use an internal Vref. As the bank is powered at 1.8V it would need to an IOSTANDARD supported for Vcco = 1.8V

 

Tablw 1-77 give the Vcco requirements for each IOSTANDARD. 

Thanks,

Sandy


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub , Versal Blogs and the Versal Useful Resources .

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View solution in original post

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mik3l3_hdl
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Registered: ‎08-15-2019

Hi,

 

I am defyining the constraints for some user defined ports of my design specifically an input clock port and input switch signal

but i do not understand which I/O standard to assign.  In the I/O standard column there is a list of I/O stadnard acronyms .  Where i can find a detailed description of those I/O standards?

 

Thanks

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Registered: ‎01-22-2015

@mik3l3_hdl 

If you are referring to the KCU105 board, then this board has a Kintex UltraScale FPGA, XCKU040.  IO standards for this FPGA are described in Xilinx documents DS892 and UG571.

Mark

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mik3l3_hdl
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Registered: ‎08-15-2019

Hi, markg@prosensing.com ,

 

thanks for replying ,

I am referring to theVirtex Ultrascale+ VCU118 Evaluation Platform (xcvu9p-flga2104-2L-e)

 

Thanks

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Registered: ‎01-22-2015

@mik3l3_hdl 

For IO standards found on the Virtex UltraScale+ of the VCU118, please refer to UG571 and DS923.

Mark