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Visitor
Visitor
811 Views
Registered: ‎05-14-2020

IBIS model Issue with Kintex Ultrascale Plus (xcku115_flvf1924)

Hi Xilinx Team,

The Kintex Ultrascale plus "kintexu_grp1.ibs" IBIS model with the buffer model of HSTL logic (HP_HSTL_I_DCI_M_OUT40) is not correct.

The device output waveform is not meeting the specified noise margins (VOH, VOL & VREF) as per the datasheet.

Also, the waveform is having lot of jitter and eye crossing is not at the Vref level.

Here is the waveform snapshot attached for reference.

1) HSTL logic [Buffer Model : HP_HSTL_I_DCI_M_OUT40 (Driver Output)]

2) HSTL logic [Buffer Model : HP_HSTL_I_DCI_M_OUT40 (with load)]

 

EYE_HP_HSTL_I_DCI_M_OUT40EYE_HP_HSTL_I_DCI_M_OUT40EYE_HP_HSTL_I_DCI_M_OUT40 (with_load)EYE_HP_HSTL_I_DCI_M_OUT40 (with_load)

 

 

 

 

 

Please share your comments at the earliest.

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9 Replies
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Xilinx Employee
Xilinx Employee
765 Views
Registered: ‎03-14-2016

Hello,

Can you please confirm your data rate?

It looks like your UI is ~350ps (~2800Mbps).  If that is true, you are running beyond the maximum speed for the HSTL IO Standard.  It is limited to 1600Mbps.

Can you please tell me if you are probing at the pin or the die?  Can you please share a capture of your setup?

Thank you,

Sam

 

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Visitor
Visitor
710 Views
Registered: ‎05-14-2020

Hi Sam,

Thank you for the response.

Yes, the data-rate is 2133 Mbps, we are trying to use RLDRAM-3 (as a load) supported with HSTL IO standard and the probing is done at die.

I would like to know, which HSTL IO standard (buffer model) will support a data rate of 2133 Mbps?
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Xilinx Employee
Xilinx Employee
637 Views
Registered: ‎03-14-2016

Hello,

I created an RLD3 example design targeting the xcku115_flvf1942 and used it to generate a custom IBIS model.  

  • The DQ, DM, QV and QK signals use HP_SSTL12_DCI_F_OUT40_IN40
  • The ADDR, BA, CK, CS, DK, DM and WE signals use HP_SSTL12_DCI_F_OUT40

Thank you,
Sam

 

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Visitor
Visitor
572 Views
Registered: ‎05-14-2020

Hi,

Thank you for the response.

But in the IBIS model for the RLD RAM, I can see it is mentioned that it supports HSTL logic.

Can I use

  • HP_HSTL12_DCI_F_OUT40DQ_IN40 for DM, QV and QK signals?
  • HP_HSTL12_DCI_F_OUT40 ADDR, BA, CK, CS, DK, DM and WE signals?

Kindly provide your feedback.

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Xilinx Employee
Xilinx Employee
564 Views
Registered: ‎03-14-2016

Hello,

You should only use the IO Standard set by the IP.  This should be SSTL12.  Can you please tell me where you are seeing HSTL associated with RLD RAM?

Thank you,

Sam

 

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Visitor
Visitor
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Registered: ‎05-14-2020

Hi,

The snapshot of the IBIS model RLDRAM3 is attached for reference.

2020-05-27_20-18-40.jpg

 

 

 

 

As provided in the comment section of the DQ model shown above, it says 1.2V HSTL I/O logic. (Same is shown for DQS with DIFF HSTL), but no I/O logics are mentioned for the Command signals or the Clock signals.

Now what is the logic I/O need to be considered at the FPGA end?

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Xilinx Employee
Xilinx Employee
505 Views
Registered: ‎03-14-2016

Hello,

This is from the RLDRAM3 device IBIS model.

The FPGA RLDRAM3 IP uses SSTL12. 

For your simulation, the FPGA will use SSTL12.  The RLDRAM3 will use HSTL.

Thank you,

Sam

 

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Visitor
Visitor
452 Views
Registered: ‎05-14-2020

Hi,

My design has Kintex ultra-scale plus FPGA "flvf1924" interfaced with two "IS49RL36320" RLD3 RAM.

The address lines follow flyby topolgy and the same is even cross checked with "UG583 design guideline".

The address lines are not meeting the thresholds. I initially doubted RLD3 RAM model, i tried models from different vendor like Micron and the same behavior is observed.

When i checked with Zynq ibis model the address lines are meeting the noise margins very vell for the same topology (ISSI part as well as Micron part).

Is there any issue with Kintex ibis model.

Address is operating at 533 MHz.

Here are the snapshot for your reference

Topology:

TopologyTopology

 

 

 

 

1) Eye probed at RLD3 Address input (@die) with Kintex "HP_SSTL12_M_OUT40" model as driver

Eye probed at RLD3 Address input (@die) with Kintex "HP_SSTL12_M_OUT40" model as driverEye probed at RLD3 Address input (@die) with Kintex "HP_SSTL12_M_OUT40" model as driver

 

 

 

 

 

 

 

 2) Eye probed at RLD3 Address input (@die) with zynq "HP_SSTL12_M_OUT40" model as driverEye probed at RLD3 Address input (@die) with zynq "HP_SSTL12_M_OUT40" model as driverEye probed at RLD3 Address input (@die) with zynq "HP_SSTL12_M_OUT40" model as driver

 

 

 

 

 


Please share your comments, your support is greatly appreciated.

Warm Regards,

Surya

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Xilinx Employee
Xilinx Employee
358 Views
Registered: ‎03-14-2016

Hello Surya,

In the Kintex captures, you are crossing the AC threshold, but you are not violating the DC threshold.

Are you running at the fast corner for these simulations?

I will work on setting up a simulation on my side to investigate this further.

Thank you,
Sam

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