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Explorer
Explorer
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Registered: ‎11-23-2013

IBUFDS_DIFF_OUT can't drive ISERDESE3 and fabric at the same time

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Hello,

I'm using VU3P device, and I need to connect the 'p' port of a differential input signal to ISERDESE3 and use a 400MHz clock to sample it at the same time, and connect the 'n' port of the same differential input signal to another ISERDESE3 to calculate the delay according to ug571.

In 7 series devices, I can use the combinational output of ISERDESE2 to do that. But in VU3P, the combinational output was removed. I have tried 2 ways to solve this problem.

1st: I use IBUFDS_DIFF_OUT and connect its 'OB' output to a IDELAYE3, then connect output of IDELAYE3 to a ISERDESE3. I also connect the 'OB' to my fabric. Using this method, following error is given.

[DRC REQP-1945] IDELAYE3.IDATAIN connected to other loads check: The IDELAYE3 cell IDELAYE3_inst1 pin IDELAYE3_inst1/IDATAIN attached to net ch_p is also connected to other loads. This is not routable because of a conflict for physical resources. Using both the delayed and undelayed version of an input port is not supported in this IDELAY configuration.

2nd: I use IBUFDS_DIFF_OUT and connect its 'OB' output to a IDELAYE3, then connect output of IDELAYE3 to a ISERDESE3. This time I use the output of IDELAYE3 to connect to my fabric. The Implementation success, but Writing Bitstream failed. The failure is caused by the un-routed nets. Neither the output of IDELAYE3 connected to my fabric nor to the ISERDESE3. 

My test code of the first way is attached below. The test code of second way just change the driver from output of IBUFDS_DIFF_OUT to output of IDELAYE3.

Is this an error of Vivado or It is designed to make the VU3P IO works that way.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/03/10 23:58:16
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
    input           sclk,
    input           clk,
    input           clk_div,
    input           ch_int_p,
    input           ch_int_n,
    input           clk_ref,
    input           rst,

    output  [ 4: 0] cnt_o,
    output  [ 7: 0] ch_q
    );

wire            clk_inv;
wire            ch_int;
wire            ch_p,ch_n;
reg     [ 4: 0] cnt;

IBUFDS_DIFF_OUT IBUFDS_DIFF_OUT_inst (
    .O(ch_p),   // 1-bit output: Buffer diff_p output
    .OB(ch_n), // 1-bit output: Buffer diff_n output
    .I(ch_int_p),   // 1-bit input: Diff_p buffer input (connect directly to top-level port)
    .IB(ch_int_n)  // 1-bit input: Diff_n buffer input (connect directly to top-level port)
);

IDELAYCTRL  #(
    .SIM_DEVICE("ULTRASCALE") )  // Must be set to "ULTRASCALE" 
idelayctrl_i(
    .REFCLK(clk_ref),
    .RST(rst),
    .RDY() );

assign clk_inv = ~clk;

IDELAYE3 #(
    .CASCADE("NONE"),          // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
    .DELAY_FORMAT("TIME"),     // Units of the DELAY_VALUE (COUNT, TIME)
    .DELAY_SRC("IDATAIN"),     // Delay input (DATAIN, IDATAIN)
    .DELAY_TYPE("VAR_LOAD"),      // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
    .DELAY_VALUE(0),           // Input delay value setting
    .IS_CLK_INVERTED(1'b0),    // Optional inversion for CLK
    .IS_RST_INVERTED(1'b0),    // Optional inversion for RST
    .REFCLK_FREQUENCY(200.0),  // IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
    .SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
                             // ULTRASCALE_PLUS_ES2)
    .UPDATE_MODE("ASYNC")      // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
)
IDELAYE3_inst1 (
    .CASC_OUT(),       // 1-bit output: Cascade delay output to ODELAY input cascade
    .CNTVALUEOUT(), // 9-bit output: Counter value output
    .DATAOUT(ch_int),         // 1-bit output: Delayed data output
    .CASC_IN(),         // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
    .CASC_RETURN(), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
    .CE(1'b0),                   // 1-bit input: Active high enable increment/decrement input
    .CLK(clk_div),                 // 1-bit input: Clock input
    .CNTVALUEIN(9'h20),   // 9-bit input: Counter value input
    .DATAIN(),           // 1-bit input: Data input from the logic
    .EN_VTC(1'b1),           // 1-bit input: Keep delay constant over VT
    .IDATAIN(ch_p),         // 1-bit input: Data input from the IOBUF
    .INC(1'b0),                 // 1-bit input: Increment / Decrement tap delay input
    .LOAD(1'b0),               // 1-bit input: Load DELAY_VALUE input
    .RST(1'b0)                  // 1-bit input: Asynchronous Reset to the DELAY_VALUE
);


ISERDESE3 #(
    .DATA_WIDTH(8),            // Parallel data width (4,8)
    .FIFO_ENABLE("FALSE"),     // Enables the use of the FIFO
    .FIFO_SYNC_MODE("FALSE"),  // Enables the use of internal 2-stage synchronizers on the FIFO
    .IS_CLK_B_INVERTED(1'b0),  // Optional inversion for CLK_B
    .IS_CLK_INVERTED(1'b0),    // Optional inversion for CLK
    .IS_RST_INVERTED(1'b0),    // Optional inversion for RST
    .SIM_DEVICE("ULTRASCALE_PLUS")  // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
                         // ULTRASCALE_PLUS_ES2)
)
ISERDESE3_inst0 (
    .FIFO_EMPTY(),           // 1-bit output: FIFO empty flag
    .INTERNAL_DIVCLK(), // 1-bit output: Internally divided down clock used when FIFO is
                                     // disabled (do not connect)

    .Q(ch_q),                             // 8-bit registered output
    .CLK(clk),                         // 1-bit input: High-speed clock
    .CLKDIV(clk_div),                   // 1-bit input: Divided Clock
    .CLK_B(clk_inv),                     // 1-bit input: Inversion of High-speed clock CLK
    .D(ch_int),                             // 1-bit input: Serial Data Input
    .FIFO_RD_CLK(1'b0),         // 1-bit input: FIFO read clock
    .FIFO_RD_EN(1'b0),           // 1-bit input: Enables reading the FIFO when asserted
    .RST(1'b0)                          // 1-bit input: Asynchronous Reset
);

assign cnt_o = cnt;
always @ (posedge sclk) begin
    if( ch_p ) cnt <= cnt + 1;
end

endmodule

 

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Accepted Solutions
Moderator
Moderator
264 Views
Registered: ‎08-08-2017

Hi @carnby 

This is not an VIVADO issue but the Ultrascale+  Device limitation.

There is dedicate route from IBUFDS_DIFF_OUT to IDELAYE3  and IDELAY3 to ISERDESE3.

Other connections are not valid considering the device architecture. 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

2 Replies
Moderator
Moderator
265 Views
Registered: ‎08-08-2017

Hi @carnby 

This is not an VIVADO issue but the Ultrascale+  Device limitation.

There is dedicate route from IBUFDS_DIFF_OUT to IDELAYE3  and IDELAY3 to ISERDESE3.

Other connections are not valid considering the device architecture. 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

Highlighted
Explorer
Explorer
245 Views
Registered: ‎11-23-2013
Thanks for your reply.
It's a pity I cannot migrate the old design to UltraScale+ deivces.
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