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crisilc
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Registered: ‎03-15-2018

ISERDES 1:4 Use with DQS

I have a design that uses ISERDESE3 in Kintex ultrascale. My design contains a source-synchronous DQ and DQS (strobe) coming from an external interface to FPGA. I am using ISERDESE3 to deserialize the data and I am using DQS as a CLK to ISERDESE3 module.  In the same design, I have an OSERDESE3 for driving external interfaces with DQ and DQS.

As per UG571, I need to connect CLKDIV. But since DQS is NOT a continuous clock, how can I connect CLKDIV port in ISERDESE3 and OSERDES3 for a DATA_WIDTH=4? And DQS direction can change during operations.

This is a fairly standard interface mechanism and hence I would appreciate it if a ready solution is provided
 
Question moved from Memory Interface to Serial Transceivers
 
 
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crisilc
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I will experiment with your suggestion. 

I have a different question regarding ISERDESE3 with EXTERNAL FIFO. It is said in ug571 that if external FIFO is used data is output from ISERDESE3 using an internally divided clock. This divided clock is available as an output but it's described as "Reserved". I would like to put a FIFO at the output of ISERDESE3, Can I used this INTERNAL_DIVCLK as FIFO write clock? In that case, do I need to connect DIVCLK using BUFGCE? 

markg@prosensing.com 

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Registered: ‎01-22-2015

@crisilc 

As you say, the INTERNAL_DIVCLK output of ISERDESE3 is "reserved" and should not be used.

Instead, as shown in Fig 2-26 of UG571(v1.12), the clock output of the BUFGCE_DIV (w/divide by 2 or 4) is sent to input, DIVCLK, of the ISERDESE3 and is also sent to a register (or an external FIFO) that captures the outputs, Q[7:0], of the ISERDESE3.  

Fig2_26_UG571.jpg

crisilc
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Registered: ‎03-15-2018

Hi Mark, 

As discussed in our last conversation, I have tried to connect ISERDESE3 with DQS_R and BUFGCE_DIV, OSERDES with DQS_S, and BUFGCE_DIV. But vivado implementation fails. 

I am receiving error like "OSERDESE and ISERDESE3 cells with a different clock which is NOT supportable"

How to proceed?

Thanks

markg@prosensing.com 

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Registered: ‎01-22-2015

@crisilc 

Please show us:

  1. a schematic from synthesis (or your sketch) of how (ISERDESE3, DQS_R, BUFGCE_DIV, OSERDES, DQS_S, and BUFGCE_DIV) are connected
  2. the exact text from the error message you have received
crisilc
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Registered: ‎03-15-2018

Hi Mark,

Apologies for the late reply. 

Xil_Com1.PNG

I am attaching the connection sketch.

The error message is like this [I have removed hierarchy from message] 

"OSERDESE and ISERDESE3 cells with a different clock which is NOT supportable"  

 

markg@prosensing.com 

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Registered: ‎01-22-2015

@crisilc 

Thank you for providing the additional information.

It appears that you are creating a SRAM interface, which uses a bidirectional DQS strobe for data capture and transmission.

Instead of creating this interface yourself, I suggest using the Xilinx IP called "AXI EMC v3.0" (see Xilinx document PG100 ) .  If you have questions about this IP or about interfacing with SRAM, please post a new question in the Memory Interfaces section of the Forum.

Cheers,
Mark

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crisilc
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Yes. I am using a bidirectional DQS for data capture and transmission. 

I am not interfacing with SRAM. I don't have address bus. Only bidirectional data bus, strobe signals and  control signals. Hence don't think that EMC will help.

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Registered: ‎01-22-2015

I am not interfacing with SRAM.

It looks like you are interfacing with some kind of external RAM.  If you do some searching, you will probably find a Xilinx IP designed for the task.  - maybe the Ultrascale Memory IP core described in document, PG150.

 

The error message is like this [I have removed hierarchy from message] 
   "OSERDESE and ISERDESE3 cells with a different clock which is NOT supportable"  

If you are still interested in developing the interface yourself and want to know more about the above error then I recommend that you start a new post with a title something like, "bidirectional IO uses both ISERDES and OSERDES".