I posted this earlier this morning, but for some reason it was flagged as spam and removed...
I have a Zynq Ultrascale+ design, and I want to have LVDS inputs into a HR bank using internal termination. UG571 (v1.11) p.126 says that this is supported if the Vcco is 2.5V (which it is), and the LVDS_25 I/O standard is used.
I have tried to do this, but the IO planning window in Vivado doesn't allow DIFF_TERM_ADV to be set for these inputs. Setting it manually in the xdc file causes the following error during placement.
[DRC PORTPROP-6] I/O standard compatibility with attribute usage: Port clk_p has property DIFF_TERM_ADV set, but its I/O Standard, LVDS_25 does not support this property.
What am I doing wrong?
Here is a minimal example. Create a new project in Vivado 2019.1 targeted towards xczu7ev-fbvb900-1-e, and add the following files. Attempting to implement the design will result in the above errror.
Top.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top is
Port ( clk_p : in STD_LOGIC;
clk_n : in STD_LOGIC;
test : out STD_LOGIC);
end top;
architecture Behavioral of top is
signal clk : std_logic;
signal test_buf : std_logic;
begin
buf : IBUFGDS
port map (
O => clk,
I => clk_p,
IB => clk_n
);
test_buf <= not test_buf when rising_edge(clk);
test <= test_buf;
end Behavioralconstraints.xdc
set_property IOSTANDARD LVCMOS33 [get_ports test]
set_property PACKAGE_PIN L15 [get_ports test]
set_property IOSTANDARD LVDS_25 [get_ports clk_p]
set_property IOSTANDARD LVDS_25 [get_ports clk_n]
set_property PACKAGE_PIN G13 [get_ports clk_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports clk_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports clk_n]
