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josh_tyler
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Registered: ‎04-10-2018

Internally terminating LVDS_25 inputs on a HR bank

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I posted this earlier this morning, but for some reason it was flagged as spam and removed...

I have a Zynq Ultrascale+ design, and I want to have LVDS inputs into a HR bank using internal termination. UG571 (v1.11) p.126 says that this is supported if the Vcco is 2.5V (which it is), and the LVDS_25 I/O standard is used.

I have tried to do this, but the IO planning window in Vivado doesn't allow DIFF_TERM_ADV to be set for these inputs. Setting it manually in the xdc file causes the following error during placement.

[DRC PORTPROP-6] I/O standard compatibility with attribute usage: Port clk_p has property DIFF_TERM_ADV set, but its I/O Standard, LVDS_25 does not support this property.

What am I doing wrong?

Here is a minimal example. Create a new project in Vivado 2019.1 targeted towards xczu7ev-fbvb900-1-e, and add the following files. Attempting to implement the design will result in the above errror.

Top.vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity top is
    Port ( clk_p : in STD_LOGIC;
           clk_n : in STD_LOGIC;
           test : out STD_LOGIC);
end top;

architecture Behavioral of top is
    signal clk : std_logic;
    signal test_buf : std_logic;
begin

    buf : IBUFGDS
    port map (
        O => clk,
        I => clk_p,
        IB => clk_n
    );
    
    test_buf <= not test_buf when rising_edge(clk);
    test <= test_buf;

end Behavioral

constraints.xdc

set_property IOSTANDARD LVCMOS33 [get_ports test]
set_property PACKAGE_PIN L15 [get_ports test]

set_property IOSTANDARD LVDS_25 [get_ports clk_p]
set_property IOSTANDARD LVDS_25 [get_ports clk_n]
set_property PACKAGE_PIN G13 [get_ports clk_p]

set_property DIFF_TERM_ADV TERM_100 [get_ports clk_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports clk_n]
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gnarahar
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Registered: ‎07-23-2015

@josh_tyler  You are using Zynq Ultrascale + device which has only HP and HD banks. No HR banks. 

HD Banks don't support DIIF_TERM. Below snippet from Page#343 of UG571 v1.11. 

hd_diff.JPG

Hence you getting the DRC

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------

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drjohnsmith
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Registered: ‎07-09-2009

A quick guess,

I think you only have to define the _P side of a diff LVDS,

   How have you created these constraints, by text or in the tools ?

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josh_tyler
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Registered: ‎04-10-2018

Yes I agree that you should only need it on one, but the tools added IOSTANDARD LVDS_25 to both, so I tried to be consistent with that.

IOSTANDARD and PACKAGE_PIN constrains were generated using Vivado I/O planning. DIFF_TERM_ADV was added manually because the I/O planning tool wouldn't let me set it.

It would implement okay without DIFF_TERM_ADV set, but I want the internal termination to be used.

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Registered: ‎01-22-2015

@josh_tyler 

IBUFGDS is not actually a valid primitive according to UG974.  Instead, try using IBUFDS, as described in UG974.

Mark

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josh_tyler
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markg@prosensing.com 

Thank you for the suggestion! I've just tried it, and it gives the same error.

Josh

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drjohnsmith
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Registered: ‎07-09-2009

I think thats a clue,

if the tools would not let you add the termination, its not valid.

 

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drjohnsmith
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Registered: ‎07-09-2009

Taking step back,

can you instantiate a different receiver, from unisim that has the option for temination on / off ?

I seem to rember there was one , but sorry I dont have vivado here to try.

 

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josh_tyler
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Registered: ‎04-10-2018

@drjohnsmith wrote:

I think thats a clue,

if the tools would not let you add the termination, its not valid.

 


I agree with you, except for the fact that Xilinx' documentation tells me it is a valid configuration (UG571 (v1.11) p.126). I think I must be configuring something incorrectly in Vivado, but I would like to know how to configure it correctly.

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josh_tyler
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Registered: ‎04-10-2018

@drjohnsmith wrote:

Taking step back,

can you instantiate a different receiver, from unisim that has the option for temination on / off ?

I seem to rember there was one , but sorry I dont have vivado here to try.

 


Good idea, I've just tried this (using IBUFDS_DIFF_OUT_INTERMDISABLE, which seems to be what you were referring to), but unfortunately it gives the same error.

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gnarahar
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Registered: ‎07-23-2015

@josh_tyler  You are using Zynq Ultrascale + device which has only HP and HD banks. No HR banks. 

HD Banks don't support DIIF_TERM. Below snippet from Page#343 of UG571 v1.11. 

hd_diff.JPG

Hence you getting the DRC

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

josh_tyler
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Registered: ‎04-10-2018

Thanks @gnarahar, I knew I must be doing something silly!

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